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tactical grade, six degrees of freedom inertial sensor data sheet ADIS16490 rev. 0 document feedbac k information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical suppor t www.analog.com features triaxial, digital gyroscope, 100/sec dynamic range 0.05 axis to axis misalignment error 0.25 axis to package misalignment error 1.8/hr in run bias stability 0.09/hr angular random walk triaxial, digital accelerometer, 8 g 3.6 g in run bias stability triaxial, delta angle and delta velocity outputs factory calibrated sensitivity, bias, and axial alignment calibration temperature range: ?40c to +85c serial peripheral interface (spi) compatible programmable operation and control automatic and manual bias correction controls 4 finite impulse response (fir) filter banks, 120 configurable taps digital input/output (i/o): data ready, external clock sample clock options: internal, external, or scaled on demand self test of inertial sensors single-supply operation: 3.0 v to 3.6 v 2000 g shock survivability operating temperature range: ?40c to +105c applications precision instrumentation, stabilization guidance, navigation, control avionics, unmanned vehicles precision autonomous machines, robotics general description the ADIS16490 is a complete inertial system that includes a triaxis gyroscope and a triaxis accelerometer. each inertial sensor in the ADIS16490 combines industry leading i mems? technology with signal conditioning that optimizes dynamic performance. the factory calibration characterizes each sensor for sensitivity, bias, alignment, and linear acceleration (gyroscope bias). as a result, each sensor has its own dynamic compensation formulas that provide accurate sensor measurements. the ADIS16490 provides a simple, cost effective method for integrating accurate, multiaxis inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. all necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. tight orthogonal alignment simplifies inertial frame alignment in navigation systems. the spi and register structure provide a simple interface for data collection and configuration control. the ADIS16490 uses the same footprint and connector system as the adis16375 , adis16480 , adis16485 , and adis16488a , which greatly simplifies the upgrade process. the ADIS16490 is packaged in a module that is approximately 47 mm 44 mm 14 mm and includes a standard connector interface. functional block diagram controller clock triaxial gyro triaxial accel power management cs sclk din dout gnd vdd temp dio1 dio2 dio3 dio4 rst spi self test i/o output data registers user control registers calibration and filters ADIS16490 15029-001 figure 1.
ADIS16490* product page quick links last content update: 11/04/2016 comparable parts view a parametric search of comparable parts evaluation kits ? adis16imu1 breakout board ? eval-adis2 evaluation system documentation data sheet ? ADIS16490: tactical grade, six degrees of freedom inertial sensor preliminary data sheet product highlight ? ADIS16490 / adis16495 / adis16497: tactical grade inertial measurement unit (imu) with industry's lowest swap+c reference materials press ? precision tactical grade mems imu delivers breakthrough system level advancements for positioning and navigation applications design resources ? ADIS16490 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ADIS16490 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ADIS16490 data sheet rev. 0 | page 2 of 37 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance ch aracteristics ............................................. 9 theory of operation ...................................................................... 12 inertial sensor signal chain ..................................................... 12 register structure ....................................................................... 13 serial peripheral interface ......................................................... 14 data ready .................................................................................. 14 reading sensor data .................................................................. 14 device configuration ................................................................ 15 user register memory map .......................................................... 16 user register defintions ................................................................ 19 gyroscope data .......................................................................... 20 acceleration data ....................................................................... 21 delta angles ................................................................................ 22 delta velocity .............................................................................. 24 calibration ................................................................................... 25 fir filters .................................................................................... 34 applications information .............................................................. 36 mounting best practices ............................................................ 36 preventing misinsertion ............................................................ 36 evaluation tools ......................................................................... 36 power supply considerations ................................................... 36 packaging and ordering information ......................................... 37 outline dimensions ................................................................... 37 ordering guide .......................................................................... 37 revision history 10/16 revision 0 : initial version
data sheet ADIS16490 rev. 0 | page 3 of 37 specifications t c = 25c, vdd = 3.3 v, angular rate = 0/sec, dynamic range = 100 /sec 1 g , unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit gyroscopes dynamic range 100 /sec sensitivity x_gyro_out and x_gyro_low (32 - bit) 7.6294 10 ?8 /sec/lsb repeatability 1 ?40c t c +85c 0.5 % sensitivity temperature coefficient ?40c t c +85c, 1 2 4 ppm/c misalignment axis to axis 0.0 5 degrees axis to frame (package) 0.25 degrees nonlinearity best fit straight line , fu ll scale ( fs ) = 100 /sec 0. 3 % fs bias repeatability 1 , 2 ?40c t c +85c, 1 0.0 5 /sec in run bas stability 1 1. 8 /hr angular random walk 1 0.09 /hr temperature coefficient ?40c t c +85c, 1 0.00 05 /sec/c linear acceleration effect any axis, 1 (config[7] = 1) 0.0 05 /sec/ g any axis, 1 (config[7] = 0) 0.015 /sec/ g vibration rectification error 0.0003 /sec/ g 2 noise output noise no filtering 0. 05 / sec rms rate noise density f = 10 hz to 40 hz, no filtering 0.00 2 /sec/hz rms ? 3 db bandwidth 480 hz sensor resonant frequency 65 khz accelerometers 3 each axis dynamic range 8 g sensitivity x_accl_out and x_accl_low (32 - bit) 7.6294 10 ?9 g /lsb repeatability 1 ?40c t c +85c 0.2 % sensitivity temperature coefficient ?40c t c +85c, 1 16 ppm/c misalignment axis to axis 0.035 degrees axis to frame (package) 0.25 degrees nonlinearity best fit straight line, 2 g 1.6 % fs best fit straight line, 4 g 0.15 % fs best fit straight line, 8 g 0.1 % fs bias repeatability 1 , 2 ?40c t c +85c, 1 3 .5 m g in run stability 1 3 .6 g velocity random walk 1 0.0 08 m/sec/hr temperature coefficient ?40c t c +85c, 1 0.0 0 8 m g /c noise output noise no filtering 0.5 m g rms noise density f = 10 hz to 40 hz, no filtering 16 g /hz rms ? 3 db bandwidth 750 hz sensor resonant frequency 2.5 khz temperature sensor scale factor output = 0x0000 at 25c (5c) 0.01429 c/lsb logic inputs 4 input voltage high, v ih 2.0 v low, v il 0.8 v rst pulse width 1 s cs wake - up pulse width 20 s
ADIS16490 data sheet rev. 0 | page 4 of 37 parameter test conditions/comments min typ max unit input current logic 1, i ih v ih = 3.3 v 10 a logic 0, i il v il = 0 v all pins except rst 10 a rst pin 0.33 ma input capacitance, c in 10 pf digital outputs 4 output voltage high, v oh i source = 0.5 ma 2.4 v low, v ol i sink = 2.0 ma 0.4 v flash memory endurance 5 100,000 cycles data retention 6 t j = 85c 20 years functional times 7 time until data is available power - on start - up time 170 ms reset recovery time 8 170 ms flash memory update time 1237 ms self test time 9 glob_cmd[1] = 1 (see table 129) 40 ms conversion rate 4.25 ksps initial clock accuracy 0.02 % temperature coefficient 40 ppm/c sync input clock 3.0 4.5 khz power supply, vdd operating voltage range 3.0 3.6 v power supply current 10 normal mode, vdd = 3.3 v, + 89 ma 1 the repeatability specifications represent a projection for long - term a ging, which is derived from the drift behaviors that a sample of units exhibited throughout their 1000- hour, 110c high temperature operating life (htol). 2 bias re peatability describes a long - term behavior over a variety of conditions. short - term repeatability relates to the in run bias stability and noise density specifications. 3 all specifications associated with the accelerometers relate to the full - scale range of 5 g. 4 the digital i/o signals use a 3.3 v system. 5 endurance is qualified as per jedec standard 22 , method a117 , measured at ?40 c , +25 c , +85 c, and +125 c . 6 the data r etention specification assumes a junction temperature (t j ) of 8 5 c per jedec s tandard 22, method a117. data r etention lifetime decreases with t j . 7 these times do not include thermal settling and in ternal filter response times, which may affect overall accuracy. 8 the rst line must be in a lo w state for at least 10 s to en sure a proper reset initiation and recovery. 9 self test time can extend when using external clock rates that are lower tha n 4000 hz. 10 supply current transients can reach 25 0 ma during initial startup or reset recovery.
data sheet ADIS16490 rev. 0 | page 5 of 37 timing specification s t c = 25c, vdd = 3.3 v, unless otherwise noted. table 2 . parameter description min 1 typ max 1 unit f sclk serial clock 0.01 15 mhz t stall 2 stall p eriod between data 2 s t cls serial clock low period 31 ns t chs serial clock high period 31 ns t cs chip select to clock edge 32 ns t dav dout valid after sclk edge 10 ns t dsu din setup time before sclk rising edge 2 ns t d hd din hold time after sclk rising edge 2 ns t dr , t df dou t rise/fall times, 100 pf loading 3 8 ns t dsoe cs assertion to data out active 0 11 ns t hd sclk edge to data out invalid 0 ns t sfs last sclk edge to cs deassertion 32 ns t dshi cs deassertion to data out high impedance 0 9 ns t nv data invalid time 11 15 s t 1 input sync pulse width 5 s t 2 input sync to data invalid 233 s t 3 input sync period 3 222.2 s 1 guaranteed by design and characterization, but not tested in production. 2 see table 3 for exceptions to the stall t ime rating . 3 thi s measurement represents th e inverse of the maximum frequency for the input sample clock: 4500 hz. register specific stall times table 3 . parameter desc ription min 1 typ max unit stall time fnctio_ctrl configure diox functions 340 s f i ltr_bnk_0 enable/select fir filter banks 65 s f i ltr_bnk_1 enable/select fir filter banks 65 s null_c n fg configure autonull bias function 71 s sync_scale configure input clock scale factor 340 s dec_rate configure decimation rate 340 s gpio_ctrl configure general - purpose i/o lines 45 s config configure miscellaneous functions 45 s glob_cmd[1] on demand self test 40 ms glob_cmd[3] flash memory update 1.24 sec glob_cmd[6] factory calibration restore 350 s glob_cmd[7] software reset 130 ms 1 monitoring the data ready signal (see table 131 for fnctio_ctrl configuration) for the return o f regular pulsing can help minimize system wait times.
ADIS16490 data sheet rev. 0 | page 6 of 37 timing diagrams cs sclk dout din 123456 1 51 6 r/w a5 a6 a4 a3 a2 d2 msb db14 d1 lsb db13 db12 db10 db11 db2 lsb db1 t cs t dshi t dr t sfs t df t dav t hd t chs t cls t dsoe t dhd t dsu 15029-002 figure 2. spi timing and sequence cs sclk t stall 15029-003 figure 3. stall time and data rate t 3 t 2 t 1 t nv dio4 (sync clock) data ready output registers data valid data valid 15029-004 figure 4. input clock timing diagram, fnctio_ctrl[7:4] = 0xfd
data sheet ADIS16490 rev. 0 | page 7 of 37 absolute maximum rat ings table 4 . parameter rating acceleration any axis, unpowered 1500 g any axis, powered 15 00 g vdd to gnd ?0.3 v to +3.6 v digital input voltage to gnd ?0.3 v to vdd + 0.2 v digital output voltage to gnd ?0.3 v to vdd + 0.2 v operating temperature range ?40c to +105c storage temperature range 1 ? 5 5c to +150c barometric pressure 2 bar 1 extended expos ure to temperatures that are lower than ? 40 c or higher than +105c can adversely affect the accuracy of the factory calibration. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect produ ct reliability. thermal resistance thermal performance is directly linked to printed circuit board ( pcb ) design and operating environment. careful attention to pcb thermal design is required. ja is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. jc is the junction to case thermal resistance. the ADIS16490 is a multi chip module, which includes many active components. the values in table 5 identify the thermal response of the hottest component inside of the ADIS16490 , with resp ect to the overall power dissipation of the module . this approach enables a simple method for predicting the temperature of the hotte st junction, bas e d on eithe r ambient or case temperature. for example, w hen the ambient temperature is 70 c, the hottest j unction inside of the ADIS16490 is 76.7 c. t j = ja v dd i dd + 70c t j = 22.8c/w 3.3 v 0.089 a + 70c t j = 76.7c table 5 . package characteristics package ty pe ja jc device weight ml -24 -9 1 30.7 c/w 20.9 c/w 4 2 g 1 thermal impedance simulated values come from a case when 4 m2 0.4 mm machine screws (torque = 20 inch - ounces) secure the adis1 6490 to the printed circuit board. esd caution
ADIS16490 data sheet rev. 0 | page 8 of 37 pin configuration and fu nction descriptions 1 dio3 sclk din dio1 dio2 vdd gnd no pin dnc dnc dnc dnc dio4 dout cs rst vdd no pin gnd dnc dnc dnc dnc dnc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ADIS16490 top view (not to scale) notes 1. this representation displays the top view pinout for the mating socket connector. 2. the actual connector pins are not visible from the top view. 3. mating connector: samtec clm-112-02 or equivalent. 4. dnc = do not connect. 5. pin 12 and pin 15 are not physically present. 15029-005 figure 5. pin configuration pin 1 pin 23 pin 1 pin 2 15029-006 figure 6. axial orientation (top side facing up) table 6. pin function descriptions pin no. mnemonic type description 1 dio3 input/output configurable digital input/output 3. 2 dio4 input/output configurable digital input/output 4. 3 sclk input spi serial clock. 4 dout output spi data output. clocks outp ut on the sclk falling edge. 5 din input spi data input. clocks inp ut on the sclk rising edge. 6 cs input spi chip select. 7 dio1 input/output configurable digital input/output 1. 8 rst input reset. 9 dio2 input/output configurable digital input/output 2. 10, 11 vdd supply power supply. 12, 15 no pin not applicable these pins are not physically present. 13, 14 gnd supply power ground. 16 to 24 dnc not applicable do not connect. do not connect to these pins.
data sheet ADIS16490 rev. 0 | page 9 of 37 typical performance characteristics 0.1 1 10 100 0.01 0.1 1 10 100 1000 10000 root allan variance (degrees/hour) tau (seconds) average + 1 ? 1 15029-307 figure 7. gyroscope root allan variance, ?0.4 ?0.2 0 0.2 0.4 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 sensitivity error (%) case temperature (c) + 3 ? 3 15029-308 figure 8. gyroscope sensitivity error, ?40c to +85c, 1c/min ?0.4 ?0.2 0 0.2 0.4 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 sensitivity error (%) case temperature (c) ? 3 15029-309 + 3 figure 9. gyroscope sensitivity error, +85c to ?40c, 1c/min case temperature (c) ?0.4 ?0.2 0 0.2 0.4 ?45?35?25?15?5 5 1525354555657585 bias error (/sec) + 3 ? 3 15029-310 figure 10. gyroscope bias error, ?40c to +85c, 1c/min case temperature (c) ?0.1 ?0.1 0 0.1 0.1 ?45?35?25?15?5 5 1525354555657585 misalignment error (degrees) + 3 ? 3 15029-313 figure 11. gyroscope axis to axis misalignment error, ?40c to +85c frequency (hz) 0.01 0.1 1 10 100 0.1 1 10 100 1k 10k gyroscope noise density (/s/ 15029-314 figure 12. gyroscope noise density, t c = 25 c
ADIS16490 data sheet rev. 0 | page 10 of 37 ?1.5 ?0.5 0 0.5 1.0 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 nonlinearity (% fs) rate (/sec) 3 x y z 15029-315 figure 13. gyrscope nonlinearity tau (seconds) 1 10 1k 100 0.1 0.01 1 10 100 1k 10k root allan variance ( g ) + 1 ? 1 15029-316 figure 14. accelerometer root allan variance, 25 c case temperature (c) ?0.20 ?0.10 ?0.15 ?0.05 0 0.10 0.20 0.05 0.15 ?45?35?25?15?5 5 1525354555657585 sensitivity error (%) + 3 ? 3 15029-317 figure 15. accelerometer sensitivity error, ?40c to +85c, 1c/min case temperature (c) ?0.20 ?0.10 ?0.15 ?0.05 0 0.10 0.20 0.05 0.15 ?45?35?25?15?5 5 1525354555657585 sensitivity error (%) + 3 ? 3 15029-318 figure 16. accelerometer sensitivity error, +85c to ?40c, 1c/min case temperature (c) ?4 ?2 ?3 ?1 0 2 4 1 3 ?45?35?25?15?5 5 1525354555657585 bias error ( m g ) + 3 ? 3 15029-319 figure 17. accelerometer bias error, ?40c to +85c, 1c/min case temperature (c) ?0.20 ?0.10 ?0.15 ?0.05 0 0.10 0.20 0.05 0.15 ?45?35?25?15?5 5 1525354555657585 misalignment error (degrees) + 3 ? 3 15029-321 figure 18. accelerometer axis to axis misalignment error, ?40c to +85c
data sheet ADIS16490 rev. 0 | page 11 of 37 ?120 ?100 ?80 ?60 ?40 ?20 0 20 20 200 2000 magnitude (db) frequency (hz) x y z 15029-322 figure 19. accelerometer vibration response (swept sine, 2 g peak) ?3 2 3 1 0 ?1 ?2 ?8 ?6 ?4 ?2 0 2 4 6 8 nonlinearity (% fs) linear force ( g ) 2 g fit 8 g fit 4 g fit 15029-323 figure 20. accelerometer nonlinearity (fit is curve fit) time from initial turn-on (minutes) ?400 ?200 ?300 ?100 0 200 400 100 300 05.0 4.5 4.0 3.5 3.0 2.5 2.0 1.2 1.0 0.5 gyroscope bias (/hour) 15029-311 +3 ?3 figure 21. gyroscope bias vs. time from initial turn-on
ADIS16490 data sheet rev. 0 | page 12 of 37 theory of operation the ADIS16490 is an autonomous sensor system that starts up on its own when it has a valid power supply. after running through its initialization process, it begins sampling, processing, and loading calibrated sensor data into the output registers, which are accessible using the spi port. inertial sensor signal chain figure 22 provides the basic signal chain for the inertial sensors in the ADIS16490 , which processes data at a rate of 4250 sps when using the internal sample clock. using one of the external clock options in fnctio_ctrl[7:4] (see table 131) can provide some flexibility in selecting this rate. mems sensors calibration filtering output data registers 15029-211 figure 22. signal processing diagram, inertial sensors gyroscope data sampling the ADIS16490 produces angular rate measurements around three orthogonal axes (x, y, and z). figure 23 shows the basic signal flow for the production of x-axis gyroscope data (same as y-axis and z-axis). this signal chain contains two digital mems gyroscopes (x g1 and x g2 ), which have their own adc and sample clocks (f sgx1 and f sgx2 = 4100 hz that produce data independently from each other. the sensor to sensor tolerance on this sample rate is 200 sps. processing this data starts with combining (summa- tion and rescale) the most recent sample from each gyroscope together by using an independent sample master frequency (f sm ) clock (f sm = 4250 hz, see figure 23), which drives the rest of the digital signal processing (calibration, alignment, and filtering) for the gyroscopes and accelerometers. mems gyroscope x g1 mems gyroscope x g2 x-axis rate data sample 1 x-axis angular rate data processing f sm = 4250hz x-axis rate data sample 2 f sgx2 = 4100hz f sgx1 = 4100hz adc adc 15029-212 figure 23. gyroscope data sampling accelerometer data sampling the ADIS16490 produces linear acceleration measurements along the same orthogonal axes (x, y, and z) as the gyroscopes, using the same clock (f sm , see figure 23 and figure 24) that triggers data acquisition and subsequent processing of the gyroscope data. accelerometer x-axis mems x-axis acceleration data processing f sm = 4250sps adc 15029-213 figure 24. accelerometer data sampling external clock options the ADIS16490 offers two modes of operation to control data production with an external clock: sync mode and pulse per second (pps) mode. in sync mode, the external clock directly controls the data sampling and production clock (f sm in figure 23 and figure 24). in pps mode, users can provide a lower input clock rate (1 hz to 128 hz) and use a scale factor (sync_scale register, see table 141) to establish a data collection and processing rate that is between 3000 hz and 4250 hz for best performance. inertial sensor calibration the calibration function for the gyroscopes and the accelerometers has two components: factory calibration and user calibration (see figure 25). from sensors to filtering factory calibration user calibration 15029-214 figure 25. gyroscope calibration processing gyroscope factory calibration gyroscope factory calibration applies the following correction formula to the data of each gyroscope: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? z y x 333231 232221 131211 z y x z y x 333231 232221 131211 zc yc xc a a a ggg ggg ggg b b b mmm mmm mmm ' ' ' (1) where: xc , yc , and zc are the postcalibration gyroscope data. m 11 , m 12 , m 13 , m 21 , m 22 , m 23 , m 31 , m 32 , and m 33 are the scale and alignment correction factors. x , y , and z are the precalibration gyroscope data. b x , b y , and b z are the bias correction factors. g 11 , g 12 , g 13 , g 21 , g 22 , g 23 , g 31 , g 32 , and g 33 are the linear g correction factors. a' x , a' y , and a' z are the postcalibration accelerometer data. all the correction factors in each matrix/array are derived from direct observation of the response of each gyroscope to a variety of rotation rates at multiple temperatures across the calibration temperature range (?40c t c +85c). these correction factors are stored in the flash memory bank, but they are not available for observation. config[7] provides an on/off control for the linear g compensation (see table 135). see figure 43 for more details on the user calibration options that are available for the gyroscopes.
data sheet ADIS16490 rev. 0 | page 13 of 37 accelerometer factory calibration the accelerometer factory calibration applies the following correction formulas to the data of each accelerometer: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 2 0 0 0 ' ' ' zc yc xc 3231 23 21 1312 z y x z y x 333231 232221 131211 z y x pp p p pp b b b a a a mmm mmm mmm a a a ? ? ? (2) where: a x , a y , and a z are the precalibration accelerometer data. a' x , a' y , and a' z are the postcalibration accelerometer data. m 11 , m 12 , m 13 , m 21 , m 22 , m 23 , m 31 , m 32 , and m 33 are the scale and alignment correction factors. b x , b y , and b z are the bias correction factors . 0 , p 12 , p 13 , p 21 , 0 , p 23 , p 31 , p 32 , and 0 are the point of percussion correction factors 2 xc , 2 yc , and 2 zc are the postcalibration gyroscope data (squared). all the correction factors in each matrix/array are derived from direct observation of the response of each accelerometer to a variety of inertial test conditions at multiple temperatures across the calibration temperature range (?40c t c +85c). these correction factors are stored in the flash memory bank, but they are not available for observation. config[6] provides an on/off control for the point of percussion alignment (see table 135). see figure 44 for more details on the user calibration options that are available for the accelerometers. filtering after calibration, the data of each inertial sensor passes through two digital filters, both of which have user configurable attributes: fir and decimation (see figure 26). from c alibration to data registers fir filter decimation filter 15029-215 figure 26. inertial sensor filtering the fir filter includes four banks of coefficients that have 120 taps each. filtr_bnk_0 (see table 143) and filtr_bnk_1 (see table 145) provide the configuration options for the use of the fir filters of each inertial sensor. each fir filter bank includes a preconfigured filter, but users can design their own filters and write over these values using the register of each coefficient. for example, table 174 provides the details for fir_coef_a071, which contains coefficient 71 in fir bank a. refer to figure 47 for the frequency response of the factory default filters. these filters do not represent any specific application environment; they are only examples. the decimation filter averages multiple samples together to produce each register update. in this type of filter structure, the number of samples in the average is equal to the reduction in the update rate for the output data registers. see the dec_rate regis- ter for the user controls for this filter (see table 137). register structure all communication with the ADIS16490 involves accessing its user registers. the register structure contains both output data and control registers. the output data registers include the latest sensor data, error flags, and identification data. the control registers include sample rate, filtering, input/output, calibration, and diagnostic configuration options. all communication between the ADIS16490 and an external processor involves either reading or writing to one of the user registers. triaxis gyro temp sensor triaxis accel dsp adc output registers control registers controller spi 15029-012 figure 27. basic operation the register structure uses a paged addressing scheme that contains 13 pages, with each page containing 64 register locations. each register is 16 bits wide, with each byte having its own unique address within the memory map of that page. the spi port has access to one page at a time, using the bit sequence in figure 28. select the page to activate for spi access by writing its code to the page_id register. read the page_id register to determine which page is currently active. table 7 displays the page_id contents for each page and their basic functions. the page_id register is located at address 0x00 on every page. table 7. user register page assignments page page_id function 0 0x00 output data, cl ock, identification 1 0x01 reserved 2 0x02 calibration 3 0x03 control: sample rate, filtering, i/o 4 0x04 serial number, crc values 5 0x05 fir filter bank a, coefficient 0 to coefficient 59 6 0x06 fir filter bank a, coefficient 60 to coefficient 119 7 0x07 fir filter bank b, coefficient 0 to coefficient 59 8 0x08 fir filter bank b, coefficient 60 to coefficient 119 9 0x09 fir filter bank c, coefficient 0 to coefficient 59 10 0x0a fir filter bank c, coefficient 60 to coefficient 119 11 0x0b fir filter bank d, coefficient 0 to coefficient 59 12 0x0c fir filter bank d, coefficient 60 to coefficient 119
ADIS16490 data sheet rev. 0 | page 14 of 37 r/w r/w a6 a5 a4 a3 a2 a1 a0 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 d0 d1d2d3d4d5d6d7 d8 d9 d10 d11d12d13 d14 d15 cs sclk din dout a6 a5 d13d14 d15 n otes 1 . dout bits are produced only when the previous 16-bit din sequence starts with r/w = 0. 2 . when cs is high, dout is in a three-state, high impedance mode, which allows multifunctional use of the line for other devices. 15029-013 figure 28. spi communication bit sequence serial peripheral interface the serial peripheral interface (spi) provides access to the user register structures and typically connects to a compatible port on an embedded processor, using the connection diagram shown in figure 29. the four spi signals facilitate synchronous, serial data communication. system processor spi master sclk cs din dout sclk ss mosi miso 3.3v irq dio2 vdd i/o lines are compatible with 3.3v logic levels 10 6 3 5 4 9 11 13 14 ADIS16490 15029-011 figure 29. electrical connection diagram table 8. generic master processor pin names and functions mnemonic function ss slave select irq interrupt request mosi master output, slave input miso master input, slave output sclk serial clock embedded processors typically use control registers to configure their serial ports for communicating with spi slave devices such as the ADIS16490 . table 9 provides a list of settings that describe the spi protocol of the ADIS16490 . the initialization routine of the master processor typically establishes these settings using firmware commands to write them into its serial control registers. table 9. generic master processor spi settings processor setting description master ADIS16490 operates as slave sclk 15 mhz maximum serial clock rate spi mode 3 cpol = 1 (polarity), cpha = 1 (phase) msb first mode bit sequence, see figure 28 for coding 16-bit mode shift register/data length data ready the factory default configuration provides users with a data ready signal on the dio2 pin, which pulses low when the output data registers are updating (see figure 30). in this configuration, connect dio2 to a pin on the embedded processor, which triggers data collection, when this signal pulses high. fnctio_ctrl[3:0] (see table 131) provides some user configuration options for this function. dio2 active inactive 15029-129 figure 30. data ready, when fn ctio_ctrl[3:0] = 1101 (default) reading sensor data reading a single register requires two 16-bit cycles on the spi: one to request the contents of a register and another to receive those contents. the 16-bit command code (see figure 28) for a read request on the spi has three parts: the read bit ( r /w = 0), either address of the register, [a6:a0], and eight dont care bits, [dc7:dc0]. figure 31 provides an example that includes two register reads in succession. this example starts with din = 0x1a00, to request the contents of the z_gyro_out register, and follows with 0x1800, to request the contents of the z_gyro_low register (assuming page_id already equals 0x0000). the sequence in figure 31 also illustrates full duplex mode of operation, which means that the ADIS16490 can receive requests on din while also transmitting data out on dout within the same 16-bit spi cycle. din dout 0x1a00 0x1800 next address z_gyro_out z_gyro_low 15029-016 figure 31. spi read example figure 32 provides an example of the four spi signals when reading the prod_id register (see table 79) in a repeating pattern. this pattern can be helpful when troubleshooting the spi interface setup and communications. sclk cs din dout dout = 0100 0000 0110 1010 = 0x406a = 16,490 (prod_id) din = 0111 1110 0000 0000 = 0x7e00 15029-017 figure 32. spi read example, second 16-bit sequence
data sheet ADIS16490 rev. 0 | page 15 of 37 device configuration each register contains 16 bits (two bytes). bits[7:0] contain the low byte and bits[15:8] contain the high byte of each register. each byte has its own unique address in the user register map (see table 10). updating the contents of a register requires writing to its low byte first and its high byte second. there are three parts to coding a spi command (see figure 28), which writes a new byte of data to a register: the write bit ( r /w = 1), the address of the byte, [a6:a0], and the new data for that location, [dc7:dc0]. figure 33 provides a coding example for writing 0xfedc to the xg_bias_low register (see table 93), assuming that page_id already equals 0x0002. s clk cs din 0x90dc 0x91fe 15029-014 figure 33. spi sequence for writing 0xfedc to xg_bias_low dual memory structure the ADIS16490 uses a dual memory structure (see figure 34), with sram supporting real-time operation and flash memory storing operational code, calibration coefficients, and user configurable register settings. the manual flash update command (glob_cmd[3], see table 129) provides a single-command method for storing user configuration settings into flash memory, for automatic recall during the next power-on or reset recovery process. this portion of the flash memory bank has two independ- ent banks that operate in a ping pong manner, alternating with every flash update. during power-on or reset recovery, the ADIS16490 performs a cyclic redundancy check (crc) on the sram and compares it to a crc computation from the same memory locations in flash memory. if this fails, the ADIS16490 resets and boots up from the other flash memory location. sys_e_flag[2] (see table 16) provides an error flag for detecting when the back-up flash memory supported the last power-on or reset recovery. table 10 provides a memory map for the user registers in the ADIS16490 , which includes flash backup support (indicated by yes or no in the flash column). nonvolatile flash memory (no spi access) manual flash backup start-up reset volatile sram spi access 15029-015 figure 34. sram and flash memory diagram
ADIS16490 data sheet rev. 0 | page 16 of 37 user register memory map table 10 . us er register memory map (n/a means not applicable) name r/w flash backup page_id address default register description page_id r/w no 0x00 0x00, 0x01 0x00 00 page identifier reserved n/a n/a 0x00 0x02, 0x03 n/a reserved data_cnt r no 0x00 0x04, 0x05 n/a da ta c ounter reserved n/a n/a 0x00 0x06, 0x07 n/a reserved sys_e_flag r no 0x00 0x08, 0x09 0x0000 output, system error flags diag_sts r no 0x00 0x0a, 0x0b 0x0000 output, self test error flags reserved n/a n/a 0x00 0x0c, 0x0d n/a reserved temp_out r no 0 x00 0x0e, 0x0f n/a output, temperature x_gyro_low r no 0x00 0x10, 0x11 n/a output, x - axis gyroscope, low word x_gyro_out r no 0x00 0x12, 0x13 n/a output, x - axis gyroscope, high word y_gyro_low r no 0x00 0x14, 0x15 n/a output, y - axis gyroscope, low word y_gyro_out r no 0x00 0x16, 0x17 n/a output, y - axis gyroscope, high word z_gyro_low r no 0x00 0x18, 0x19 n/a output, z - axis gyroscope, low word z_gyro_out r no 0x00 0x1a, 0x1b n/a output, z - axis gyroscope, high word x_accl_low r no 0x00 0x1c, 0x1d n/a o utput, x - axis accelerometer, low word x_accl_out r no 0x00 0x1e, 0x1f n/a output, x - axis accelerometer, high word y_accl_low r no 0x00 0x20, 0x21 n/a output, y - axis accelerometer, low word y_accl_out r no 0x00 0x22, 0x23 n/a output, y - axis accelerometer , high word z_accl_low r no 0x00 0x24, 0x25 n/a output, z - axis accelerometer, low word z_accl_out r no 0x00 0x26, 0x27 n/a output, z - axis accelerometer, high word time_stamp r no 0x00 0x28, 0x29 n/a output, time stamp reserved n/a n/a 0x00 0x28 to 0x3 f n/a reserved x_deltang_low r no 0x00 0x40, 0x41 n/a output, x - axis delta angle, low word x_deltang_out r no 0x00 0x42, 0x43 n/a output, x - axis delta angle, high word y_deltang_low r no 0x00 0x44, 0x45 n/a output, y - axis delta angle, low word y_deltang _out r no 0x00 0x46, 0x47 n/a output, y - axis delta angle, high word z_deltang_low r no 0x00 0x48, 0x49 n/a output, z - axis delta angle, low word z_deltang_out r no 0x00 0x4a, 0x4b n/a output, z - axis delta angle, high word x_deltvel_low r no 0x00 0x4c, 0x 4d n/a output, x - axis delta velocity, low word x_deltvel_out r no 0x00 0x4e, 0x4f n/a output, x - axis delta velocity, high word y_deltvel_low r no 0x00 0x50, 0x51 n/a output, y - axis delta velocity, low word y_deltvel_out r no 0x00 0x52, 0x53 n/a output, y - axis delta velocity, high word z_deltvel_low r no 0x00 0x54, 0x55 n/a output, z - axis delta velocity, low word z_deltvel_out r no 0x00 0x56, 0x57 n/a output, z - axis delta velocity, high word reserved n/a n/a 0x00 0x58 to 0x7 d n/a reserved prod_id r ye s 0x00 0x7e, 0x7f 0x406 a output, product identification (16,4 90 ) reserved n/a n/a 0x01 0x00 to 0x7 f n/a reserved page_id r/w no 0x02 0x00, 0x01 0x00 00 page identifier reserved n/a n/a 0x02 0x02, 0x03 n/a reserved x_gyro_scale r/w yes 0x02 0x04, 0x05 0x 0000 calibration, scale, x - axis gyroscope y_gyro_scale r/w yes 0x02 0x06, 0x07 0x0000 calibration, scale, y - axis gyroscope z_gyro_scale r/w yes 0x02 0x08, 0x09 0x0000 calibration, scale, z - axis gyroscope x_accl_scale r/w yes 0x02 0x0a, 0x0b 0x0000 calib ration, scale, x - axis accelerometer y_accl_scale r/w yes 0x02 0x0c, 0x0d 0x0000 calibration, scale, y - axis accelerometer z_accl_scale r/w yes 0x02 0x0e, 0x0f 0x0000 calibration, scale, z - axis accelerometer xg_bias_low r/w yes 0x02 0x10, 0x11 0x0000 cali bration, bias , gyroscope, x - axis, low word xg_bias_high r/w yes 0x02 0x12, 0x13 0x0000 calibration, bias, gyroscope, x - axis, high word yg_bias_low r/w yes 0x02 0x14, 0x15 0x0000 calibration, bias, gyroscope, y - axis, low word yg_bias_high r/w yes 0x02 0x 16, 0x17 0x0000 calibration, bias, gyroscope, y - axis, high word
data sheet ADIS16490 rev. 0 | page 17 of 37 name r/w flash backup page_id address default register description zg_bias_low r/w yes 0x02 0x18, 0x19 0x0000 calibr ation, bias, gyroscope, z-axis, low word zg_bias_high r/w yes 0x02 0x1a, 0x1b 0x0000 calibr ation, bias, gyroscope, z-axis, high word xa_bias_low r/w yes 0x02 0x1c, 0x1d 0x0000 calibration, bias, accelerometer, x-axis, low word xa_bias_high r/w yes 0x02 0x1e, 0x1f 0x0000 calibration, bias, accelerometer, x-axis, high word ya_bias_low r/w yes 0x02 0x20, 0x21 0x0000 calibration, bias, accelerometer, y-axis, low word ya_bias_high r/w yes 0x02 0x22, 0x23 0x0000 calibration, bias, accelerometer, y-axis, high word za_bias_low r/w yes 0x02 0x24, 0x25 0x0000 calibration, bias, accelerometer, z-axis, low word za_bias_high r/w yes 0x02 0x26, 0x27 0x0000 calibration, bias, accelerometer, z-axis, high word reserved n/a n/a 0x02 0x28 to 0x73 0x0000 reserved user_scr_1 r/w yes 0x02 0x74, 0x75 0x0000 user scratch register 1 user_scr_2 r/w yes 0x02 0x76, 0x77 0x0000 user scratch register 2 user_scr_3 r/w yes 0x02 0x78, 0x79 0x0000 user scratch register 3 user_scr_4 r/w yes 0x02 0x7a, 0x7b 0x0000 user scratch register 4 flshcnt_low r yes 0x02 0x7c, 0x7d n/a diagnostic, flash memory count, low word flshcnt_high r yes 0x02 0x7e, 07f n/a diagnostic, flash memory count, high word page_id r/w no 0x03 0x00, 0x01 0x0000 page identifier glob_cmd w no 0x03 0x02, 0x03 n/ a control, global commands reserved n/a n/a 0x03 0x04, 0x05 n/a reserved fnctio_ctrl r/w yes 0x03 0x06, 0x07 0x000d co ntrol, i/o pins, functional definitions gpio_ctrl r/w yes 0x03 0x08, 0x09 0x00x0 1 control, i/o pins, general purpose config r/w yes 0x03 0x0a, 0x0b 0x00c0 contro l, clock, and miscellaneous correction dec_rate r/w yes 0x03 0x0c, 0x0d 0x0000 cont rol, output sample rate decimation null_cnfg r/w yes 0x03 0x0e, 0x0f 0x070a control, automatic bias correction configuration sync_scale r/w yes 0x03 0x10, 0x11 0x 109a input clock scaling (pps mode) reserved n/a n/a 0x03 0x12 to 0x15 n/a reserved filtr_bnk_0 r/w yes 0x03 0x16, 0x17 0x0000 filter selection filtr_bnk_1 r/w yes 0x03 0x18, 0x19 0x0000 filter selection reserved n/a n/a 0x03 0x1a to 0x77 n/a reserved firm_rev r yes 0x03 0x78, 0x79 n/a firmware revision firm_dm r yes 0x03 0x7a, 0x7b n/a fi rmware programming date: day/month firm_y r yes 0x03 0x7c, 0x7d n/a firmware programming date: year boot_rev r yes 0x03 0x7e, 0x7f n/a boot loader revision page_id r/w no 0x04 0x00, 0x01 0x0000 page identifier reserved n/a n/a 0x04 0x02, 0x03 n/a reserved cal_sigtr_lwr r yes 0x04 0x04, 0x05 n/a signature crc, calibration coefficients, low word cal_sigtr_upr r yes 0x04 0x06, 0x07 n/a signature crc, calibration coefficients, high word cal_drvtn_lwr r no 0x04 0x08, 0x09 n/a real-time crc, calibration coefficients, low word cal_drvtn_upr r no 0x04 0x0a, 0x0b n/a real-time crc, calibration coefficients, high word code_sigtr_lwr r yes 0x04 0x0c, 0x0d n/a signature crc, program code, low word code_sigtr_upr r yes 0x04 0x0e, 0x0f n/a signature crc, program code, high word code_drvtn_lwr r no 0x04 0x10, 0x11 n/a real-time crc, program code, low word code_drvtn_upr r no 0x04 0x12, 0x13 n/a re al-time crc, program code, high word reserved n/a n/a 0x04 0x1c to 0x1f n/a reserved serial_num r yes 0x04 0x20, 0x21 n/a serial number reserved n/a n/a 0x04 0x22 to 0x7f n/a reserved page_id r/w no 0x05 0x00, 0x01 0x0000 page identifier reserved n/a n/a 0x05 0x02 to 0x07 n/a reserved fir_coef_axxx 2 r/w yes 0x05 0x08 to 0x7f n/a fir filter bank a: coefficient 0 through coefficient 59 page_id r/w no 0x06 0x00 0x0000 page identifier reserved n/a n/a 0x06 0x02 to 0x07 n/a reserved fir_coef_axxx 2 r/w yes 0x06 0x08 to 0x7f n/a fir filter ban k a: coefficient 60 through coefficient 119 page_id r/w no 0x07 0x00 0x0000 page identifier
ADIS16490 data sheet rev. 0 | page 18 of 37 name r/w flash backup page_id address default register description reserved n/a n/a 0x07 0x02 to 0x07 n/a reserved fir_coef_bxxx 3 r/w yes 0x07 0x08 to 0x7f n/a fir filter bank b: coefficient 0 through coefficient 59 page_id r/w no 0x08 0x00 0x0000 page identifier reserved n/a n/a 0x08 0x02 to 0x07 n/a reserved fir_coef_bxxx 3 r/w yes 0x08 0x08 to 0x7f n/a fir filter ban k b: coefficient 60 through coefficient 119 page_id r/w no 0x09 0x00 0x0000 page identifier reserved n/a n/a 0x09 0x02 to 0x07 n/a reserved fir_coef_cxxx 4 r/w yes 0x09 0x08 to 0x7f n/a fir filter bank c: coefficient 0 through coefficient 59 page_id r/w no 0x0a 0x00 0x0000 page identifier reserved n/a n/a 0x0a 0x 02 to 0x07 n/a reserved fir_coef_cxxx 4 r/w yes 0x0a 0x08 to 0x7f n/a fir filter bank c: coefficient 60 through coefficient 119 page_id r/w no 0x0b 0x00 0x0000 page identifier reserved n/a n/a 0x0b 0x 02 to 0x07 n/a reserved fir_coef_dxxx 5 r/w yes 0x0b 0x08 to 0x7f n/a fir filter bank d: coefficient 0 through coefficient 59 page_id r/w no 0x0c 0x00 0x0000 page identifier reserved n/a n/a 0x0c 0x02 to 0x07 n/a reserved fir_coef_dxxx 5 r/w yes 0x0c 0x08 to 0x7f n/a fir filter bank d: coefficient 60 through coefficient 119 1 the gpio_ctrl[7:4] bits reflect the logic levels on the diox lines and do not have a default setting. 2 see the fir filter bank a, fir_coef_a000 to fir_coef_a119 sectio n for additional information. 3 see the fir filter bank b, fir_coef_b000 to fir_coef_b119 sectio n for additional information. 4 see the fir filter bank c, fir_coef_c000 to fir_coef_c119 sectio n for additional information. 5 see the fir filter bank d, fir_coef_d000 to fir_coef_d119 section for addional information.
data sheet ADIS16490 rev. 0 | page 19 of 37 user register defint ions page number (page_id) table 11 . page_id register definition page addresses default access flash backup 0x00 0x00, 0x01 0x0000 r/w no table 12 . page_id bit assignments bits description [15:0] page number, binary numerical format the contents in the page_id register (see table 11 and table 12 ) contain the current page setting , and provide a control for selecting another page for spi access. for example, set din = 0x8002 to select page 2 for spi - based user access. see table 10 for the page assignments associated with each user accessible register. data/sample counter (data_cnt) table 13 . data_cnt register definition page addresses default access flash backup 0x00 0x04, 0x05 not applicable r no table 14 . data_cnt bit assignments bits description [15:0] data counter, b inary format. the data_cnt register (see table 13 and table 14 ) is a continu - ou s, real - time, sample counter. it starts at 0x0000, increments every time that the output data registers update, and wraps around from 0xffff (65 ,535 decimal ) to 0x0000 (0 decimal ) status/error flag indicators (sys_e_flag) table 15 . sys_e_f lag register definition page addresses default access flash backup 0x00 0x08, 0x09 0x0000 r no table 16 . sys_e_flag bit assignments bits description 15 watch dog timer flag. a 1 indicates that the ADIS16490 automatically reset s itself to clear an issue. [14: 9 ] not used . 8 sync error. a 1 indicates that the sample timing is not scaling correctly, when operating in pps mode (fnctio_ctrl [8] = 1, see table 131 ). when this error occurs, v erify that the input sync frequency is correct and that sync_scal e (see table 141 ) has the correct value. 7 processing overrun. a 1 indicates occurrence of a processi ng overrun. initiate a reset to recover. replace the ADIS16490 if this error persists. 6 flash memory update failure. a 1 indicates that the most recent flash memory update failed (glob_cm d[3], see table 129 ). repeat t he t est and replace the ADIS16490 if this error persists. 5 sensor failure. a 1 indicates fail ure of the self test processes (glob_cmd[1], see table 129 ), when the device is not in motion. replace the ADIS16490 if the error persists. 4 not used . 3 spi communication error. a 1 indicates that the total number of sclk cycles is not equal to a n integer multiple of 16. repeat the previous communication sequence to recover. persistence in this error may indicate a weakness in the spi service from the master processor. 2 sram error condition. a 1 indicates a failure in the crc (period = 20 ms) between the sram and flash memory. initiate a reset to recover and replace the ADIS16490 if this error persists. 1 boot memo ry failure. a 1 indicates that the crc on the primary flash memory bank did not match the reference crc value and t hat the device automatically re booted using the backup memory bank in flash. replace the ADIS16490 if this error persists. 0 not used . the sys_e_flag register (see table 15 and table 16 ) provides various error flags. reading this register causes all of its bits to return to 0 , with the exception of bit 7. if an error condition persists, its flag (bit) automatically returns to an alarm value of 1.
ADIS16490 data sheet rev. 0 | page 20 of 37 self test error flags (diag_sts) table 17. diag_sts register definition page addresses default access flash backup 0x00 0x0a, 0x0b 0x0000 r no table 18. diag_sts bit definitions bits description (default = 0x0000) [15:6] not used 5 self test failure, z-axis accelerometer (1 = failure) 4 self test failure, y-axis accelerometer (1 = failure) 3 self test failure, x-axis accelerometer (1 = failure) 2 self test failure, z-axis gyroscope (1 = failure) 1 self test failure, y-axis gyroscope (1 = failure) 0 self test failure, x-axis gyroscope (1 = failure) sys_e_flag[5] (see table 16) contains the pass/fail result (0 = pass) for the on demand self test (odst) operations, whereas the diag_sts register (see table 17 and table 18) contains pass/fail flags (0 = pass) for each inertial sensor. reading the diag_sts register causes all of its bits to restore to 0. the bits in diag_sts return to 1 if the error conditions persists. internal temperature (temp_out) table 19. temp_out register definition page addresses default access flash backup 0x00 0x0e, 0x0f not applicable r no table 20. temp_out bit definitions bits description [15:0] temperature data; twos complement, 1c per 70 lsb, 25c = 0x0000 the temp_out register (see table 19 and table 20) provides a coarse measurement of the temperature inside of the ADIS16490 . this data is most useful for monitoring relative changes in the thermal environment. table 21. temp_out data format examples temperature (c) decimal hex binary +85 +4200 0x1068 0001 0000 0110 1000 +25 + 2/70 +2 0x0002 0000 0000 0000 0010 +25 + 1/70 +1 0x0001 0000 0000 0000 0001 +25 0 0x0000 0000 0000 0000 0000 +25 C 1/70 ?1 0xffff 1111 1111 1111 1111 +25 C 2/70 ?2 0xfffe 1111 1111 1111 1110 ?40 ?4550 0xee3a 1110 1110 0011 1010 gyroscope data the gyroscopes in the ADIS16490 measure the angular rate of rotation around three orthogonal axes (x, y, and z). figure 35 illustrates the orientation of each gyroscope axis, along with the direction of rotation that produces a positive response in each of their measurements. pin 1 pin 23 y y-axis x x-axis z-axis z 15029-018 figure 35. gyroscope axis and polarity assignments each gyroscope has two output data registers. figure 36 illustrates how these two registers combine to support a 32-bit, twos complement data format for the x-axis gyroscope measurements. this format also applies to the y- and z-axes as well. x-axis gyroscope data 015 15 0 x_gyro_out x_gyro_low 15029-019 figure 36. gyroscope ou tput data structure x-axis gyroscope (x_gyro_low, x_gryo_out) table 22. x_gyro_low register definition page addresses default access flash backup 0x00 0x10, 0x11 not applicable r no table 23. x_gyro_low bit definitions bits description [15:0] x-axis gyroscope data; low word table 24. x_gyro_out register definition page addresses default access flash backup 0x00 0x12, 0x13 not applicable r no table 25. x_gyro_out bit definitions bits description [15:0] x-axis gyroscope data; high word; twos complement, 100/sec range; 0/sec = 0x0000, 1 lsb = 0.005/sec the x_gyro_low (see table 22 and table 23) and x_gryo_ out (see table 24 and table 25) registers contain the gyroscope data for the x-axis.
data sheet ADIS16490 rev. 0 | page 21 of 37 y-axis gyroscope (y_gyro_low, y_gyro_out) table 26. y_gyro_low register definition page addresses default access flash backup 0x00 0x14, 0x15 not applicable r no table 27. y_gyro_low bit definitions bits description [15:0] y-axis gyroscope data; low word table 28. y_gyro_out register definition page addresses default access flash backup 0x00 0x16, 0x17 not applicable r no table 29. y_gyro_out bit definitions bits description [15:0] y-axis gyroscope data; high word; twos complement, 100/sec range; 0/sec = 0x0000, 1 lsb = 0.005/sec the y_gyro_low (see table 26 and table 27) and y_gryo_ out (see table 28 and table 29) registers contain the gyroscope data for the y-axis. z-axis gyroscope (z_gyro_low, z_gyro_out) table 30. z_gyro_low register definition page addresses default access flash backup 0x00 0x18, 0x19 not applicable r no table 31. z_gyro_low bit definitions bits description [15:0] z-axis gyroscope data; additional resolution bits table 32. z_gyro_out register definition page addresses default access flash backup 0x00 0x1a, 0x1b not applicable r no table 33. z_gyro_out bit definitions bits description [15:0] z-axis gyroscope data; high word; twos complement, 100/sec range; 0/sec = 0x0000, 1 lsb = 0.005/sec the z_gyro_low (see table 30 and table 31) and z_gryo_ out (see table 32 and table 33) registers contain the gyroscope data for the z-axis. gyroscope resolution table 34 and table 35 offer various numerical examples that demonstrate the format of the angular rate (gyroscopes) data in both 16-bit and 32-bit formats. table 34. 16-bit gyroscope data format examples rotation rate (/sec) decimal hex binary +100 +20,000 0x4e20 0100 1110 0010 0000 +0.01 +2 0x0002 0000 0000 0000 0010 +0.005 +1 0x0001 0000 0000 0000 0001 0 0 0x0000 0000 0000 0000 0000 ?0.005 ?1 0xffff 1111 1111 1111 1111 ?0.01 ?2 0xfffe 1111 1111 1111 1110 ?100 ?20,000 0xb1e0 1011 0001 1110 0000 table 35. 32-bit gyroscope data format examples rotation rate (/sec) decimal hex +100 +1,310,720,000 0x4e200000 +0.005/2 15 +2 0x00000002 +0.005/2 16 +1 0x00000001 0 0 0x0000000 ?0.005/2 16 ?1 0xffffffff ?0.005/2 15 ?2 0xfffffffe ?100 ?1,310,720,000 0xb1e00000 acceleration data the accelerometers in the ADIS16490 measure both dynamic and static (response to gravity) acceleration along three orthogonal axes (x, y, and z). figure 37 illustrates the orientation of each accelerometer axis, along with the direction of acceleration that produces a positive response in each of their measurements. pin 1 pin 23 a y y-axis x-axis a x z-axis a z 15029-020 figure 37. accelerometer axis and polarity assignments each accelerometer has two output data registers. figure 38 illustrates how these two registers combine to support a 32-bit, twos complement data format for the x-axis accelerometer measurements. this format also applies to the y- and z-axes. x-axis accelerometer data 015 15 0 x_accl_out x_accl_low 15029-021 figure 38. accelerometer output data structure
ADIS16490 data sheet rev. 0 | page 22 of 37 x-axis accelerometer (x_accl_low, x_accl_out) table 36. x_accl_low register definition page addresses default access flash backup 0x00 0x1c, 0x1d not applicable r no table 37. x_accl_low bit definitions bits description [15:0] x-axis accelerometer data; low word table 38. x_accl_out register definition page addresses default access flash backup 0x00 0x1e, 0x1f not applicable r no table 39. x_accl_out definitions bits description [15:0] x-axis accelerometer data, high word; twos complement, 8 g range; 0 g = 0x0000, 1 lsb = 0.5 m g the x_accl_low (see table 36 and table 37) and x_accl_ out (see table 38 and table 39) registers contain the accelerome- ter data for the x-axis. y-axis accelerometer (y _accl_low, y_accl_out) table 40. y_accl_low register definition page addresses default access flash backup 0x00 0x20, 0x21 not applicable r no table 41. y_accl_low bit definitions bits description [15:0] y-axis accelerometer data; low word table 42. y_accl_out register definition page addresses default access flash backup 0x00 0x22, 0x23 not applicable r no table 43. y_accl_out bit definitions bits description [15:0] y-axis accelerometer data, high word; twos complement, 8 g range, 0 g = 0x0000, 1 lsb = 0.5 m g the y_accl_low (see table 40 and table 41) and y_accl_ out (see table 42 and table 43) registers contain the accelerome- ter data for the y-axis. z-axis accelerometer (z _accl_low, z_accl_out) table 44. z_accl_low register definition page addresses default access flash backup 0x00 0x24, 0x25 not applicable r no table 45. z_accl_low bit definitions bits description [15:0] z-axis accelerometer data; low word table 46. z_accl_out register definition page addresses default access flash backup 0x00 0x26, 0x27 not applicable r no table 47. z_accl_out bit definitions bits description [15:0] z-axis accelerometer data, high word; twos complement, 8 g range; 0 g = 0x0000, 1 lsb = 0.5 m g the z_accl_low (see table 44 and table 45) and z_accl_ out (see table 46 and table 47) registers contain the accelerome- ter data for the z-axis. accelerometer resolution table 48 and table 49 offer various numerical examples that demonstrate the format of the linear acceleration data in both 16-bit and 32-bit formats. table 48. 16-bit accelerometer data format examples acceleration decimal hex binary +8 g +16,000 0x3e80 0011 1110 1000 0000 +1.0 m g +2 0x0002 0000 0000 0000 0010 +0.5 m g +1 0x0001 0000 0000 0000 0001 0 m g 0 0x0000 0000 0000 0000 0000 ?0.5 m g ?1 0xffff 1111 1111 1111 1111 ?1.0 m g ?2 0xfffe 1111 1111 1111 1110 ?8 g ?16,000 0xc180 1100 0001 1000 0000 table 49. 32-bit accelerometer data format examples acceleration decimal hex +8 g +1,048,576,000 0x3e800000 +0.1/2 15 m g +2 0x00000002 +0.5/2 16 m g +1 0x00000001 0 m g 0 0x00000000 ?0.5/2 16 m g ?1 0xffffffff ?0.1/2 15 m g ?2 0xfffffffe ?8 g ?1,048,576,000 0xc1800000 delta angles in addition to the angular rate of rotation (gyroscope) measure- ments around each axis (x, y, and z), the ADIS16490 also provides delta angle measurements that represent a computation of angular displacement between each sample update. pin 1 pin 23 ? y y-axis ? x x-axis z-axis ? z 15029-022 figure 39. delta angle axis and polarity assignments
data sheet ADIS16490 rev. 0 | page 23 of 37 the delta angle outputs represent an integration of the gyro- scope measurements and use the following formula for all three axes (x-axis displayed): ?? ? ? ? ?? ? ? ??? 1 0 1, , , 2 1 d d ddnxddnx s dnx f ?? ? where: d is the decimation rate = dec_rate + 1 (see table 137). f s is the sample rate. d is the incremental variable in the summation formula. x is the x-axis rate of rotation (gyroscope). n is the sample time, prior to the decimation filter. when using the internal sample clock, f s is equal to 4250 sps. when using the external clock option, f s is equal to the frequency of the external clock. the range in the delta angle registers accommodates the maximum rate of rotation (100 /sec), the nominal sample rate (4250 sps) and an update rate of 1 hz (dec_rate = 0x1099; divide by 4249 plus 1, see table 137), all at the same time. when using an external clock that is higher than 4250 sps, reduce the dec_rate setting to avoid over- ranging the delta angle registers. each axis of the delta angle measurements has two output data registers. figure 40 illustrates how these two registers combine to support a 32-bit, twos complement data format for the x-axis delta angle measurements. this format also applies to the y- and z-axes. x-axis delta angle data 015 15 0 x_deltang_out x_deltang_low 15029-025 figure 40. delta angle output data structure x-axis delta angle (x_deltang_low, x_deltang_out) table 50. x_deltang_low register definitions page addresses default access flash backup 0x00 0x40, 0x41 not applicable r no table 51. x_deltang_low bit definitions bits description [15:0] x-axis delta angle data; low word table 52. x_deltang_out register definitions page addresses default access flash backup 0x00 0x42, 0x43 not applicable r no table 53. x_deltang_out bit definitions bits description [15:0] x-axis delta angle data, high word; twos complement, 720 range, 0 = 0x0000, 1 lsb = 720/2 15 = ~0.022 the x_deltang_low (see table 50 and table 51) and x_deltang_out (see table 52 and table 53) registers contain the delta angle data for the x-axis. y-axis delta angle (y_deltang_low, y_deltang_out) table 54. y_deltang_low register definitions page addresses default access flash backup 0x00 0x44, 0x45 not applicable r no table 55. y_deltang_low bit definitions bits description [15:0] y-axis delta angle data; low word table 56. y_deltang_out register definitions page addresses default access flash backup 0x00 0x46, 0x47 not applicable r no table 57. y_deltang_out bit definitions bits description [15:0] y-axis delta angle data, high word; twos complement, 720 range, 0 = 0x0000, 1 lsb = 720/2 15 = ~0.022 the y_deltang_low (see table 54 and table 55) and y_deltang_out (see table 56 and table 57) registers contain the delta angle data for the y-axis. z-axis delta angle (z_deltang_low, z_deltang_out) table 58. z_deltang_low register definitions page addresses default access flash backup 0x00 0x48, 0x49 not applicable r no table 59. z_deltang_low bit definitions bits description [15:0] z-axis delta angle data; low word table 60. z_deltang_out register definitions page addresses default access flash backup 0x00 0x4a, 0x4b not applicable r no table 61. z_deltang_out bit definitions bits description [15:0] z-axis delta angle data, high word; twos complement, 720 range, 0 = 0x0000, 1 lsb = 720/2 15 = ~0.022 the z_deltang_low (see table 58 and table 59) and z_deltang_out (see table 60 and table 61) registers contain the delta angle data for the z-axis.
ADIS16490 data sheet rev. 0 | page 24 of 37 delta angle resolution table 62 and table 63 offer various numerical examples that demonstrate the format of the delta angle data in both 16-bit and 32-bit formats. table 62. 16-bit delta angle data format examples delta angle () decimal hex binary +720 (2 15 ? 1)/2 15 +32,767 0x7fff 0111 1111 1110 1111 +720/2 14 +2 0x0002 0000 0000 0000 0010 +720/2 15 +1 0x0001 0000 0000 0000 0001 0 0 0x0000 0000 0000 0000 0000 ?720/2 15 ?1 0xffff 1111 1111 1111 1111 ?720/2 14 ?2 0xfffe 1111 1111 1111 1110 ?720 ?32,768 0x8000 1000 0000 0000 0000 table 63. 32-bit delta angle data format examples delta angle () decimal hex +720 (2 31 ? 1)/2 31 +2,147,483,647 0x7fffffff +720/2 30 +2 0x00000002 +720/2 31 +1 0x00000001 0 0 0x00000000 ?720/2 31 ?1 0xffffffff ?720/2 30 ?2 0xfffffffe ?720 ?2,147,483,647 0x80000000 delta velocity in addition to the linear acceleration measurements along each axis (x, y, and z), the ADIS16490 also provides delta velocity measurements that represent a computation of linear velocity change between each sample update. pin 1 pin 23 ? v y y-axis x-axis ? v x z-axis ? v z 15029-024 fi gure 41. delta velocity axis and polarity assignments the delta velocity outputs represent an integration of the accelera- tion measurements and use the following formula for all three axes (x-axis displayed): ?? ? ? ? ?? ? ? ??? 1 0 1, , , 2 1 d d ddnxddnx s dnx aa f v where: d is the decimation rate = dec_rate + 1 (see table 137). f s is the sample rate. d is the incremental variable in the summation formula. a x is the x-axis rate of rotation (gyroscope). n is the sample time, prior to the decimation filter. when using the internal sample clock, f s is equal to 4250 sps. when using the external clock option, f s is equal to the frequency of the external clock. the range in the delta velocity registers accommodates the maximum linear acceleration (8 g ), the nominal sample rate (4250 sps) and an update rate of 1 hz (dec_rate = 0x1099; divide by 4249 plus 1, see table 137), all at the same time. when using an external clock that is higher than 4250 sps, reduce the dec_rate setting to avoid overranging the delta velocity registers. e ach axis of the d elta velocity measurements has two output data registers. figure 42 illustrates how these two registers combin e to s upport 32-bit, two s complement d ata fo rmat fo r the delta v elocity measurements alo ng t he x- axis. t his f ormat also a pplies to t he y- and x-axes. x-axis delta velocity data 015 15 0 x_ deltvel_out x_ deltvel_low 15029-025 fi gure 42. delta angle output data structure x-axis delta velocity (x_deltvel_low, x_deltvel_out) table 64. x_deltvel_low register definitions page addresses default access flash backup 0x00 0x4c, 0x4d not applicable r no table 65. x_deltvel_low bit definitions bits description [15:0] x-axis delta angle data; low word table 66. x_deltvel_out register definitions page addresses default access flash backup 0x00 0x4e, 0x4f not applicable r no table 67. x_deltvel_out bit definitions bits description [15:0] x-axis delta velocity data; twos complement, 200 m/sec range, 0 m/sec = 0x0000; 1 lsb = 200 m/sec 2 15 = ~6.104 mm/sec the x_deltvel_low (see table 64 and table 65) and x_deltvel_out (see table 66 and table 67) registers contain the delta velocity data for the x-axis. y-axis delta velocity (y_deltvel_low, y_deltvel_out) table 68. y_deltvel_low register definitions page addresses default access flash backup 0x00 0x50, 0x51 not applicable r no table 69. y_deltvel_low bit definitions bits description [15:0] y-axis delta angle data; low word table 70. y_deltvel_out register definitions page addresses default access flash backup 0x00 0x52, 0x53 not applicable r no
data sheet ADIS16490 rev. 0 | page 25 of 37 table 71. y_deltvel_out bit definitions bits description [15:0] y-axis delta velocity data, high word; twos complement, 200 m/sec range, 0 m/sec = 0x0000; 1 lsb = 200 m/sec 2 15 = ~6.104 mm/sec the y_deltvel_low (see table 68 and table 69) and y_deltvel_out (see table 70 and table 71) registers contain the delta velocity data for the y-axis. z-axis delta velocity (z_deltvel_low, z_deltvel_out) table 72. z_deltvel_low register definitions page addresses default access flash backup 0x00 0x54, 0x55 not applicable r no table 73. z_deltvel_low bit definitions bits description [15:0] z-axis delta angle data; low word table 74. z_deltvel_out register definitions page addresses default access flash backup 0x00 0x56, 0x57 not applicable r no table 75. z_deltvel_out bit definitions bits description [15:0] z-axis delta velocity data, high word; twos complement, 200 m/sec range, 0 m/sec = 0x0000; 1 lsb = 200 m/sec 2 15 = ~6.104 mm/sec the z_deltvel_low (see table 72 and table 73) and z_deltvel_out (see table 74 and table 75) registers contain the delta velocity data for the z-axis. delta velocity resolution table 76 and table 77 offer various numerical examples that demonstrate the format of the delta angle data in both 16-bit and 32-bit formats. table 76. 16-bit delta velocity data format examples velocity (m/sec) decimal hex binary +200 (2 15 ? 1)/2 15 +32,767 0x7fff 0111 1111 1110 1111 +200/2 14 +2 0x0002 0000 0000 0000 0010 +200/2 15 +1 0x0001 0000 0000 0000 0001 0 0 0x0000 0000 0000 0000 0000 ?200/2 15 ?1 0xffff 1111 1111 1111 1111 ?200/2 14 ?2 0xfffe 1111 1111 1111 1110 ?200 ?32,768 0x8000 1000 0000 0000 0000 table 77. 32-bit delta angle data format examples velocity (m/sec) decimal hex +200 (2 31 ? 1)/2 31 +2,147,483,647 0x7fffffff +200/2 30 +2 0x00000002 +200/2 31 +1 0x00000001 0 0 0x00000000 ?200/2 31 ?1 0xffffffff ?200/2 30 ?2 0xfffffffe ?200 ?2,147,483,648 0x80000000 product identification, prod_id table 78. prod_id register definitions page addresses default access flash backup 0x00 0x7e, 0x7f 0x406a r yes table 79. prod_id bit definitions bits description [15:0] product identification = 0x406a the prod_id register (see table 78 and table 79) contains the numerical portion of the part number (16490). see figure 32 for an example of how to use a looping read of this register to validate the integrity of the communication. calibration the signal chain of each inertial sensor (accelerometers, gyro- scopes) includes application of unique correction formulas that come from extensive characterization of bias, sensitivity, align- ment, and response to linear acceleration (gyroscopes) over a temperature range of ?40c to +85c for the ADIS16490 . these correction formulas are not accessible, but users do have the opportunity to adjust the bias and the scale factor, for each sensor individually, through user accessible registers. these correction factors follow immediately after the factory derived correction formulas in the signal chain, which processes at a rate of 4250 hz when using the internal sample clock (see f sm in figure 23 and figure 24) calibration, gyroscope scale, x_gyro_scale table 80. x_gyro_scale register definitions page addresses default access flash backup 0x02 0x04, 0x05 0x0000 r/w yes table 81. x_gyro_scale bit definitions bits description [15:0] x-axis gyroscope scale correction; twos complement, 0x0000 = unity gain, 1 lsb = 1 2 15 = ~0.003052% the x_gyro_scale register (see table 80 and table 81) provides users with the opportunity to adjust the scale factor for the x-axis gyroscopes. see figure 43 for an illustration of how this scale factor influences the x-axis gyroscope data. x-axis gyro factory calibration and filtering x_gyro_out x_gyro_low xg_bias_high xg_bias_low 1 + x_gyro_scale 15029-026 figure 43. user calibration signal path, gyroscopes
ADIS16490 data sheet rev. 0 | page 26 of 37 calibration, gyroscope scale, y_gyro_scale table 82. y_gyro_scale register definitions page addresses default access flash backup 0x02 0x06, 0x07 0x0000 r/w yes table 83. y_gyro_scale bit definitions bits description [15:0] y-axis gyroscope scale correction; twos complement, 0x0000 = unity gain, 1 lsb = 1 2 15 = ~0.003052% the y_gyro_scale register (see table 82 and table 83) allows users to adjust the scale factor for the y-axis gyroscopes. this register influences the y-axis gyroscope measurements in the same manner that x_gyro_scale influences the x-axis gyroscope measurements (see figure 43). calibration, gyroscope scale, z_gyro_scale table 84. z_gyro_scale register definitions page addresses default access flash backup 0x02 0x08, 0x09 0x0000 r/w yes table 85. z_gyro_scale bit definitions bits description [15:0] z-axis gyroscope scale correction; twos complement, 0x0000 = unity gain, 1 lsb = 1 2 15 = ~0.003052% the z_gyro_scale register (see table 84 and table 85) allows users to adjust the scale factor for the z-axis gyroscopes. this register influences the z-axis gyroscope measurements in the same manner that x_gyro_scale influences the x-axis gyroscope measurements (see figure 43). calibration, accelerometer scale, x_accl_scale table 86. x_accl_scale register definitions page addresses default access flash backup 0x02 0x0a, 0x0b 0x0000 r/w yes table 87. x_accl_scale bit definitions bits description [15:0] x-axis accelerometer scale correction; twos complement, 0x0000 = unity gain, 1 lsb = 1 2 15 = ~0.003052% the x_accl_scale register (see table 86 and table 87) allows users to adjust the scale factor for the x-axis accelerometers. see figure 44 for an illustration of how this scale factor influences the x-axis accelerometer data. x-axis accl factory calibration and filtering x_accl_out x_accl_low xa_bias_high xa_bias_low 1 + x_accl_scale 15029-027 figure 44. user calibration signal path, accelerometers calibration, accelerometer scale, y_accl_scale table 88. y_accl_scale register definitions page addresses default access flash backup 0x02 0x0c, 0x0d 0x0000 r/w yes table 89. y_accl_scale bit definitions bits description [15:0] y-axis accelerometer scale correction; twos complement, 0x0000 = unity gain, 1 lsb = 1 2 15 = ~0.003052% the y_accl_scale register (see table 88 and table 89) allows users to adjust the scale factor for the y-axis accelerometers. this register influences the y-axis accelerometer measurements in the same manner that x_accl_scale influences the x-axis accelerometer measurements (see figure 44). calibration, acceleromete r scale, z_accl_scale table 90. z_accl_scale register definitions page addresses default access flash backup 0x02 0x0e, 0x0f 0x0000 r/w yes table 91. z_accl_scale bit definitions bits description [15:0] z-axis accelerometer scale correction; twos complement, 0x0000 = unity gain, 1 lsb = 1 2 15 = ~0.003052% the z_accl_scale register (see table 90 and table 91) allows users to adjust the scale factor for the z-axis accelerometers. this register influences the z-axis accelerometer measurements in the same manner that x_accl_scale influences the x-axis accelerometer measurements (see figure 44). calibration, gyroscope bias, xg_bias_low, xg_bias_high table 92. xg_bias_low register definitions page addresses default access flash backup 0x02 0x10, 0x11 0x0000 r/w yes table 93. xg_bias_low bit definitions bits description [15:0] x-axis gyroscope offset correction, low word; twos complement, 0/sec = 0x0000, 1 lsb = 0.005/sec 2 16 table 94. xg_bias_high register definitions page addresses default access flash backup 0x02 0x12, 0x13 0x0000 r/w yes table 95. xg_bias_high bit definitions bits description [15:0] x-axis gyroscope offset correction, high word; twos complement, 0/sec = 0x0000, 1 lsb = 0.005/sec the xg_bias_low (see table 92 and table 93) and xg_ bias_high (see table 94 and table 95) registers combine to allow users to adjust the bias of the x-axis gyroscopes. the digital format examples in table 34 also apply to the xg_bias_high register, and the digital format examples in table 35 apply to the
data sheet ADIS16490 rev. 0 | page 27 of 37 number that comes from combining the xg_bias_low and xg_bias_high registers . see figure 43 for an illustration of how these two registers combine and influence the x - axis gyroscope measurements. calibration, gyroscope bias, y g_bias_low, yg_bias_high table 96 . yg_bias_low register definitions page addresses default access flash backup 0x02 0x14, 0x15 0x0000 r/w yes table 97 . yg_bias_low bit definitions bits description [15:0] y - axis gyroscope offset correction, low word; twos complement, 0/sec = 0x0000, 1 lsb = 0.005/sec 2 16 table 98 . yg_bias_high register definitions page addresses default access flash backup 0x02 0x16, 0x17 0x0000 r/w yes table 99 . yg_bias_high bit definitions bits description [15:0] y - axis gyroscope offset correction, high word; twos complement, 0/sec = 0x0000, 1 lsb = 0.0 05 /sec the yg_bias_low (see table 96 and table 97 ) and yg_ bias_high (see table 98 and table 99 ) registers combine to allow users to adjust the bias of the y - axis gyroscopes. the digital format examples in table 34 also apply to the yg_bias_high register, and the digital format examples in table 35 apply to the number that comes from combining the yg_bias_low and yg_bias_high registers . these register s influences the y - axis gyroscope measurements in the same manner that the xg_bias_ low and xg_bias_high registers influ ence the x - axis gyroscope measurements (see figure 43). calibration, gyroscope bias, zg_bias_low, zg_bias_hig h table 100 . zg_bias_low register definitions page addresses default access flash backup 0x02 0x18, 0x19 0x0000 r/w yes table 101 . zg_bias_low bit definitions bits description [15:0] z - axis gyroscope offs et correction, low word; twos complement, 0/sec = 0x0000, 1 lsb = 0.005/sec 2 16 table 102 . zg_bias_high register definitions page addresses default access flash backup 0x02 0x1a, 0x1b 0x0000 r/w yes table 103 . zg_bias_high bit definitions bits description [15:0] z - axis gyroscope offset correction, high word twos complement, 0/sec = 0x0000, 1 lsb = 0.0 05 /sec the zg_bias_low (see table 100 and table 101 ) and zg_ bias_high (see table 102 and table 103 ) registers combine to allow users to adjust the bias of the z - axis gyroscopes. the digital format examples in table 34 also apply to the zg_bias_high register, and the digital format examples in table 35 apply to the number that comes from combining the zg_bias_low and zg_bias_high registers . these registers influence the z - axis gyroscop e measurements in the same manner that the xg_bias_ low and xg_bias_high registers influence the x - axis gyroscope measurements (see figure 43). calibration, accelerometer bias, xa_bias_low, xa_bias_high table 104 . xa_bias_low register definitions page addresses default access flash backup 0x02 0x1c, 0x1d 0x0000 r/w yes table 105 . xa_bias_low bit definitions bits description [15:0] x - axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 lsb = 0.5 m g 2 16 table 106 . xa_bias_high register definitions page addresses default access flash backup 0x02 0x1e, 0x1f 0x0000 r/w yes table 107 . xa_bias_high bit defini tions bits description [15:0] x - axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 lsb = 0.5 m g the xa_bias_low (see table 104 and table 105 ) and xa_ bias_high (see table 106 and table 107 ) registers combine to allow users to adjust the bias of the x - axis accelerometers. the digital format examples in table 48 also apply to the xa_bias_ high regi ster and the digital format examples in table 49 apply to the number that comes from combining the xa_bias_low and xa_bias_high registers . see figure 44 for an illustration of how these tw o registers combine and influence the x - axis gyroscope measurements. calibration, accelerometer bias, ya_bias_low, ya_bias_high table 108 . ya_bias_low register definitions page addresses default access flash backup 0x02 0x20, 0x21 0x0000 r/w yes table 109 . ya_bias_low bit definitions bits description [15:0] y - axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 lsb = 0. 5 m g 2 16 table 110 . ya_bias_high register definitions page addresses default access flash backup 0x02 0x22, 0x23 0x0000 r/w yes
ADIS16490 data sheet rev. 0 | page 28 of 37 table 111 . ya_bias_high bit definitions bits description [15:0] y - axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 lsb = 0. 5 m g the ya_bias_low (see table 108 and table 109 ) and ya _ bias_high (see table 110 and table 111 ) registers combine to allow us ers to adjust the bias of the y - axis accelerometers. the digital format examples in table 48 also apply to the ya_bias_ high register, and the digital format examples in table 49 apply to the number that comes from combining the ya_bias_low and ya_bias_high registers . these registers influence the y - axis accelerometer measurements in the same manner that the xa_bias_low and xa_bias_high registers influence the x - axis accelerometer measurem ents (see figure 44). calibration, accelerometer bias, za_bias_low, za_bias_high table 112 . za_bias_low register definitions page addresses default access flash backup 0x02 0x24, 0x25 0x0000 r/w yes table 113 . za_bias_low bit definitions bits description [15:0] z - axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 lsb = 0.5 m g 2 16 table 114 . za_bias_high register definition s page addresses default access flash backup 0x02 0x26, 0x27 0x0000 r/w yes table 115 . za_bias_high bit definitions bits description [15:0] z - axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 lsb = 0.5 m g the za_bias_low (see table 112 and table 113 ) and za_ bias_high (see table 114 and table 115 ) registers combine to allow users to adjust the b ias of the z - axis accelerometers. the digital format examples in table 48 also apply to the za_ bias_ high register and the digital format examples in table 49 apply to the number that come s from combining the za_bias_low and za_bias_high registers . these registers influence the z - axis accelerometer measurements in the same manner that the xa_bias_low and xa_bias_high registers influence the x - axis accelerometer measurements (see figure 44). scratch registers, user_scr_x table 116 . user_scr_1 register definitions page addresses default access flash backup 0x02 0x74, 0x75 0x0000 r/w yes table 117 . user_scr_1 bit defin itions bits description [15:0] user defined table 118 . user_scr_2 register definitions page addresses default access flash backup 0x02 0x76, 0x77 0x0000 r/w yes table 1 19 . user_scr_2 bit definitions bits description [15:0] user defined table 120 . user_scr_3 register definitions page addresses default access flash backup 0x02 0x78, 0x79 0x0000 r/w yes table 121 . user_scr_3 bit definitions bits description [15:0] user defined table 122 . user_scr_4 register definitions page addresses default access flash backup 0x02 0x7a, 0x7b 0x0000 r/w yes table 123 . user_scr_4 bit definitions bits description [15:0] user defined the user_scr_1 (see table 116 and table 117 ), user_scr_2 (see table 118 and table 119 ), user_scr_3 (see table 120 an d table 121 ), user_scr_4 (see table 122 and table 123 ) registers provide four locations for users to store information. flash mem ory endurance counter, flshcnt_low, flshcnt_high table 124 . flshcnt_low register definitions page addresses default access flash backup 0x02 0x7c, 0x7d not applicable r yes table 125 . flshcnt_low bit defini tions bits description [15:0] flash memory write counter, low word table 126 . flshcnt_high register definitions page addresses default access flash backup 0x02 0x7e, 0x7f not applicable r yes table 127 . f lshcnt_high bit definitions bits description [15:0] flash memory write counter, high word the flshcnt_low (see table 124 and table 125 ) and flshcnt_high (see table 126 and table 127 ) registers combine to provide a 32 - bit, binary counter that tracks the number of flash memory write cycles. in addition to the number of write cycles, the flash memory has a finite service lifetime, which depends on the junction temperature. figure 45 provides some guidance for estimating the retention life for the flash memory at specific junction temperatures. the junction temperature is approximately 7c above the case temperature.
data sheet ADIS16490 rev. 0 | page 29 of 37 600 450 300 150 0 30 40 retention (years) junction temperature (c) 55 70 85 100 125 135 150 15029-028 figure 45. flash memory retention global commands, glob_cmd table 128. glob_cmd register definitions page addresses default access flash backup 0x03 0x02, 0x03 not applicable w no table 129. glob_cmd bit definitions bits description [15:8] not used 7 software reset 6 factory calibration restore [5:4] not used 3 flash memory update 2 not used 1 self test 0 bias correction update the glob_cmd register (see table 128 and table 129) provides trigger bits for several operations. write a 1 to the appropriate bit in glob_cmd to start a particular function. software reset turn to page 3 (din = 0x8003) and then set glob_cmd[7] = 1 (din = 0x8280, din = 0x8300) to initiate a reset in the operation of the ADIS16490 . this reset removes all data, initializes all registers from their flash settings, and restarts data sampling and processing. this function provides a firmware alternative to providing a low pulse on the rst pin (see table 6, pin 8). factory calibration restore turn to page 3 (din = 0x8003) and then set glob_cmd[6] = 1 (din = 0x8240, din = 0x8300) to initiate restoration of the factory calibration. this restoration writes 0x0000 to the following registers: x_gyro_scale, y_gyro_ scale, z_gyro_scale, x_accl_scale, y_accl_ scale, z_accl_scale, xg_bias_low, xg_bias_high, yg_bias_ low, yg_bias_high, zg_bias_low, zg_bias_ high, xa_bias_low, xa_bias_high, ya_bias_low, ya_bias_ high, za_bias_low, and za_bias_high. flash memory update turn to page 3 (din = 0x8003) and then set glob_cmd[3] = 1 (din = 0x8208, din = 0x8300) to initiate a manual flash update. sys_e_flag[6] (see table 16) identifies success (0) or failure (1) in completing this process. on demand self test (odst) turn to page 3 (din = 0x8003) and then set glob_cmd[1] = 1 (din = 0x8202, then din = 0x8300) to run the odst routine, which executes the following steps: 1. measure the output on each sensor. 2. activate an internal force on the mechanical elements of each sensor, which simulates the force associated with actual inertial motion. 3. measure the output response on each sensor. 4. deactivate the internal force on each sensor. 5. calculate the difference between the force on and normal operating conditions (force off). 6. compare the difference with internal pass/fail criteria. 7. report the pass/fail results for each sensor in diag_sts (see table 18) and the overall pass/fail flag in sys_e_flag[5] (see table 16). false positive results are possible when the executing the odst while the device is in motion. bias correction update turn to page 3 (din = 0x8003) and set glob_cmd[0] = 1 (din = 0x8201, then din = 0x8300) to update the user offset registers with the correction factors of the cbe (see table 139). ensure that the inertial platform is stable during the entire average time for optimal bias estimates. auxiliary i/o line configuration, fnctio_ctrl table 130. fnctio_ctrl register definitions page addresses default access flash backup 0x03 0x06, 0x07 0x000d r/w yes table 131. fnctio_ctrl bit definitions bits description [15:9] not used 8 sync clock mode: 1 = pps, 0 = sync 7 sync clock input enable: 1 = enabled, 0 = disabled 6 sync clock input polarity: 1 = rising edge, 0 = falling edge [5:4] sync clock input line selection: 00 = dio1, 01 = dio2, 10 = dio3, 11 = dio4 3 data ready enable: 1 = enabled, 0 = disabled 2 data ready polarity: 1 = positive, 0 = negative [1:0] data ready line selection: 00 = dio1, 01 = dio2, 10 = dio3, 11 = dio4 the fnctio_ctrl register (see table 130 and table 131) provides configuration control for each i/o pin (dio1, dio2, dio3, and dio4). each diox pin supports only one function at a time. when a single pin has two assignments, the enable bit
ADIS16490 data sheet rev. 0 | page 30 of 37 for the lower priority function automatically resets to zero (disabling the lower p riority function). the order of priority is as follows, from highest priority to lowest priority: data ready, sync clock inpu t, and general - purpose. the ADIS16490 can take up to 20 ms to ex ecute a write command to the fnctio_ctrl register. during this time, the operational state and the contents of the register remain unchanged, but the spi interface supports normal communication (for accessing other registers). data ready indicator the fnct io_ctrl[3:0] bits provide three configuration options for the data ready function: on/off, polarity, and diox line. the primary purpose this signal is to drive the interrupt control line of an embedded processor, which can help synchronize data collection and minimize latency. the factory default assigns dio2 as a positive polarity, data ready signal, which means that the data in the output registers is valid when the dio2 line is high (see figure 30 ). this configuration works well when dio2 drives an interrupt service pin that activates on a low to high pulse. use the following sequence to change this assignment to dio 3 with negative polarity: 1. turn to page 3 (din = 0x8003) . 2. set fnctio_ctrl[3:0] = 1000 (din = 0x860 a , then din = 0x 8700). the timing jitter on the data ready signal is typically within 1.4 s. when using dio1 to support the data ready function, this signal can experience some premature pulses, which do not indicate that data production has started , during its start - u p process. if it is necessary to use dio1 for this function, use it in conjunction with a delay or other control mechanism to prevent prem ature data acquisition activity during the start - up process. input sync/cl ock control the fnctio_ctrl[8 :4] bits provid e several configuration options for using one of the diox lines as an external clock signal and for controlling inertial sensor data collection and processing. for example, use the following sequence to establish dio4 as a pos itive polarity, input clock pi n that operate s in s ync mode and preserve s the factory default setting for the data ready function: 1. turn to page 3 (din = 0x8003) . 2. set fnctio_ctrl[7:0] = 0xfd (din = 0x86fd ) . 3. set fnctio_ctrl[15:8] = 0x00 ( din = 0x8700). in sync mode, the ADIS16490 disable s its internal sample clock , and the frequency of the external clock signal establish es the rate of data collection and processing ( f sm in figure 23 and figure 24) . when using the pps m ode (f nctio_ctrl[8] = 1 ) the rate of data collection and production (f sm ) is equal to the product of the external clock frequency and scale factor (k ecsf ) in the sync_scale register ( see table 141). general - purpose i/o control, gpio_ctrl table 132 . gpio_ctrl register definitions 1 page addresses default access flash backup 0x03 0x08, 0x09 0x00x0 r/w yes 1 the gpio_ctrl[7:4] bits reflect the logic levels on the diox lines and do not have a default setting. table 133 . gpio_ctrl bit definitions 1 bits description [15:8] dont care 7 general - purpose i/o line 4 (dio4) data level 6 general - purpose i/o line 3 (dio3) data level 5 general - purpose i/o line 2 (dio2) data level 4 general - purpose i/o line 1 (dio1) data level 3 general - purpose i/o line 4 (dio4) direction control (1 = output, 0 = input) 2 general - purpose i/o line 3 (dio3) direction control (1 = output, 0 = input) 1 general - p urpose i/o line 2 (dio2) direction control (1 = output, 0 = input) 0 general - purpose i/o line 1 (dio1) direction control (1 = output, 0 = input) 1 the gpio_ctrl[7:4] bits reflect the logic levels on the diox lines and do not have a default setting. whe n fnctio_ctrl does not configure a diox pin, the gpio_ctrl register (see table 132 and table 133) provides user controls for general - purpose use of the diox pin s. gpio_ctrl[3:0] provide input/output assig nment controls for each line. when the diox lines are inputs, monitor their level by reading gpio_ctrl[7:4]. when the diox lines are used as outputs, set their level by writing to gpio_ctrl[7:4]. for example, use the following sequence to set dio1 and dio3 as high and low output lines, respectively, and set dio2 and dio4 as input lines. turn to page 3 (din = 0x8003) and set gpio_ ctrl[7:0] = 0x15 (din = 0x8815, then din = 0x8900). miscellaneous configuration, config table 134 . config register definitions page addresses default access flash backup 0x03 0x0 a , 0x0 b 0x00c0 r/w yes table 135 . config bit definitions bits description [15:8] not used 7 linear g compensation for gyroscopes (1 = enabled) 6 point of percussion alignment (1 = enabled) [5:0] not used the config register (see table 134 and table 135 ) provides configuration options for the linear g compensa tion in the gyroscopes (on/off) and the point of percussion alignment for the accelerometers (on/off ) .
data sheet ADIS16490 rev. 0 | page 31 of 37 point of percussion config[6] offers a point of percussion alignment function that maps the accelerometer sensors to the corner of the package identified in figure 46. to activate this feature, turn to page 3 (din = 0x8003), then set config[6] = 1 (din = 0x8a40, din = 0x8b00). pin 1 pin 23 point of percussion alignment reference point. see config[6]. 15029-029 figure 46. point of percussion reference point linear acceleration on effect on gyroscope bias the ADIS16490 includes first-order compensation for the linear g effect in the gyroscopes, which uses the following model: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a a a lglglg lglglg lglglg zpc ypc xpc z y x 33 32 31 23 22 21 13 12 11 zc yc xc the linear g correction factors, lg xy , apply correction for linear acceleration in all three directions to the data path of each gyro- scope ( xpc , ypc , and zpc ) at the rate of the data samples (4250 sps when using the internal clock). config[7] provides an on/off control for this compensation. the factory default value for this bit activates this compensation. to turn it off, turn to page 3 (din = 0x8003) and set config[7] = 0 (din = 0x8a40, din = 0x8b00). note that this command sequence also preserves the default setting for the point of percussion alignment function (on). decimation filter, dec_rate table 136. dec_rate register definitions page addresses default access flash backup 0x03 0x0c, 0x0d 0x0000 r/w yes table 137. dec_rate bit definitions bits description [15:11] dont care [10:0] decimation rate, binary format, maximum = 4249 the dec_rate register (see table 136 and table 137) provides user control for the final filter stage (see figure 26), which averages and decimates the accelerometers and gyroscopes data, while also extending the time that the delta angle and delta velocity track between each update. the output sample rate is equal to 4250/(dec_rate + 1). for example, turn to page 3 (din = 0x8003), and set dec_rate = 0x2a (din = 0x8c2a, then din = 0x8d00) to reduce the output sample rate to ~98.8 sps (4250 43). data update rate in external sync modes when using the input sync option, in direct mode (fnctio_ ctrl[8:7] = 01, see table 131), replace the 4250 number in this relationship with the input clock frequency. when using the input sync option, in pps mode (fnctio_ctrl[8:7] = 11, see table 131), replace the 4250 number in this relationship with the product of the input sync frequency and the scale value in the sync_scale register (see table 141). continuous bias estimation (cbe), null_cnfg table 138. null_cnfg register definitions page addresses default access flash backup 0x03 0x0e, 0x0f 0x070a r/w yes table 139. null_cnfg bit definitions bits description [15:14] not used 13 z-axis acceleration bias correction enable (1 = enabled) 12 y-axis acceleration bias correction enable (1 = enabled) 11 x-axis acceleration bias correction enable (1 = enabled) 10 z-axis gyroscope bias correction enable (1 = enabled) 9 y-axis gyroscope bias correction enable (1 = enabled) 8 x-axis gyroscope bias correction enable (1 = enabled) [7:4] not used [3:0] time base control (tbc), range: 0 to 13 (default = 10); t b = 2 tbc /4250, time base; t a = 64 t b , average time the null_cnfg register (see table 138 and table 139) provides the configuration controls for the continuous bias estimator (cbe), which associates with the bias correction update command in glob_cmd[0] (see table 129). null_cnfg[3:0] establishes the total average time (t a ) for the bias estimates and null_cnfg[13:8] provide on/off controls for each sensor. the factory default configuration for null_cnfg enables the bias null command for the gyroscopes, disables the bias null command for the accelerometers, and sets the average time to ~26.64 sec. when a sensor bit in null_cnfg is active (equal to 1), setting glob_cmd[0] = 1 (din sequence: 0x8003, 0x8201, 0x8300) causes its bias correction register to automatically update with a value that corrects for its present bias error (from the cbe). for example, setting null_cnfg[8] equal to 1 causes an update in the xg_bias_low (see table 93) and xg_bias_high (see table 95) registers. scaling the input clock (pps mode), sync_scale table 140. sync_scale register definitions page addresses default access flash backup 0x03 0x10, 0x11 0x109a r/w yes table 141. sync_scale bit definitions bits description [15:0] external clock scale factor (k ecsf ), binary format
ADIS16490 data sheet rev. 0 | page 32 of 37 the pps mode (fnctio_ctrl[8] = 1, see table 131) supports the use of an input sync frequency that is slower than the data sample rat es of the inertial sensors. this mode supports a frequency range of 1 hz to 128 hz for the input sync mode. in this mode, the data sample rate is equal to the product of the value in the sync_scale register (see table 140 and table 141 ) and the input sync frequency. for example, the following command sequence set s the data collection and processing rate (f sm in figure 23 and figure 24 ) to 4000 hz ( sync_sc ale = 0x0fa0) when using a 1 hz signal on the dio3 line as the external clock input, while also preserving the factory default configuration for the data ready signal: 1. turn to page 3 (din = 0x8003) . 2. set sync_scale [7:0] = 0xa0 (din = 0x90a0) . 3. set sync_scal e [15:8] = 0x0f (din = 0x910f) . 4. set fnctio_ctrl[7:0] = 0xfd (din = 0x86 e d). 5. set fnctio_ctrl[15:8] = 0x00 (din = 0x870 1 ). fir filter control, filtr_bnk_0, filtr_bnk_1 table 142 . filtr_bnk_0 register definitions page addresses default access flash backup 0x03 0x16, 0x17 0x0000 r/w yes table 143 . filtr_bnk_0 bit definitions bits description (default = 0x0000) 15 dont care 14 y - axis accelerometer filter enable (1 = enabled) [13:12] y - axis accelerometer filte r bank selection: 00 = bank a, 01 = bank b, 10 = bank c, 11 = bank d 11 x - axis accelerometer filter enable (1 = enabled) [10:9] x - axis accelerometer filter bank selection: 00 = bank a, 01 = bank b, 10 = bank c, 11 = bank d 8 z - axis gyroscope filter enable (1 = enabled) [7:6] z - axis gyroscope filter bank selection: 00 = bank a, 01 = bank b, 10 = bank c, 11 = bank d 5 y - axis gyroscope filter enable (1 = enabled) [4:3] y - axis gyroscope filter bank selection: 00 = bank a, 01 = bank b, 10 = bank c, 11 = bank d 2 x - axis gyroscope filter enable (1 = enabled) [1:0] x - axis gyroscope filter bank selection: 00 = bank a, 01 = bank b, 10 = bank c, 11 = bank d table 144 . filtr_bnk_1 register definitions page addresses default acc ess flash backup 0x03 0x18, 0x19 0x0000 r/w yes table 145 . filtr_bnk_1 bit definitions bits description [15:3] dont care 2 z - axis accelerometer filter enable (1 = enabled) [1:0] z - axis accelerometer filter bank selection: 00 = bank a, 01 = bank b, 10 = bank c, 11 = bank d the filtr_bnk_0 (see table 142 and table 143 ) and filtr_ bnk_1 (see table 144 and table 145 ) registers provide the configuration controls for the fir filter bank in the signal chain of each sensor (see figure 26). these registers provide on/off control for the fir bank for each inertial sensor, along with the fir bank (a, b, c, or d) that each sensor uses. firmware revision, firm_rev table 146 . firm_rev register definitions page addresses default access flash backup 0x03 0x78, 0x79 not applicable r yes table 147 . firm_rev bit defin itions bits description [15:12] firmware revision binary coded decimal (bcd) code, tens digit, numerical format = 4 - bit binary, range = 0 to 9 [11:8] firmware revision bcd code, ones digit, numerical format = 4 - bit binary, range = 0 to 9 [7:4] firmware revision bcd code, tenths digit, numerical format = 4 - bit binary, range = 0 to 9 [3:0] firmware revision bcd code, hundredths digit, numerical format = 4 - bit binary, range = 0 to 9 the firm_rev register (see table 146 and table 147 ) provides the firmware revision for the internal firmware. this register uses a bcd format, where each nibble represents a digit. for example, if firm_rev = 0x1234, the firmware revision is 12.34. firmware revision day and mo nth, firm_dm table 148 . firm_dm register definitions page addresses default access flash backup 0x03 0x7a, 0x7b not applicable r yes table 149 . firm_dm bit definitions bits description [15:12] factory conf iguration month bcd code, tens digit, numerical format = 4 - bit binary, range = 0 to 2 [11:8] factory configuration month bcd code, ones digit, numerical format = 4 - bit binary, range = 0 to 9 [7:4] factory configuration day bcd code, tens digit, numerical format = 4 - bit binary, range = 0 to 3 [3:0] factory configuration day bcd code, ones digit, numerical format = 4 - bit binary, range = 0 to 9 the firm_dm register (see table 148 and table 149 ) contains t he month and day of the factory configuration date. firm_ dm[15:12] and firm_dm[11:8] contain digits that represent the month of the factory configuration in a bcd format. for example, november is the 11 th month in a year and is represented by firm_dm[15:8 ] = 0x11. firm_ dm[7:4] and firm_dm[3:0] contain digits that represent the day of factory configuration in a bcd format. for example, the 27 th day of the month is represented by firm_dm[7:0] = 0x27.
data sheet ADIS16490 rev. 0 | page 33 of 37 firmware revision year, firm_y table 150 . firm_y register definitions page addresses default access flash backup 0x03 0x7c, 0x7d not applicable r yes table 151 . firm_y bit definitions bits description [15:12] factory configuration year bcd code, thousands dig it, numerical format = 4 - bit binary, range = 0 to 9 [11:8] factory configuration year bcd code, hundreds digit, numerical format = 4 - bit binary, range = 0 to 9 [7:4] factory configuration year bcd code, tens digit, numerical format = 4 - bit binary, range = 0 to 3 [3:0] factory configuration year bcd code, ones digit, numerical format = 4 - bit binary, range = 0 to 9 the firm_y register (see table 150 and table 151 ) contains the year of the factory configu ration date. for example, the year 2013 is represented by firm_y = 0x2013. boot revision number, boot_rev table 152 . boot_rev register definitions page addresses default access flash backup 0x03 0x7e, 0x7f not applicable r yes tab le 153 . boot_rev bit definitions bits description [15:8] binary, major revision number [7:0] binary, minor revision number continuous sram testing this device employs a crc function on the sram memory blocks that contain the prog ram code (code_sigtr_xxx) and the calibration coefficients (cal_drvtn_xxx). this process operates in the background and generates real - time , 32- bit crc values fo r the program code and calibration coefficients, respectively. at the conclusion of each cycle, the processor writes these calculated values in the cal_drvtn_xxx and code_drvtn_xxx registers (see table 159, table 161 , table 167 , and table 169 ) and compares them with the signature values, which reflect the state of these memory locations at the time of factory configuration. when the calculation results do not match the signature values, sys_e_ flag[2] increases to a 1. the respective signature valu es are available for user access through the cal_sigtr_xxx and code_sigtr_xxx registers (see table 155 , table 157 , table 163 , and table 165 ). the follow ing conditions must be met for sys_e_flag[2] to remain at the zero level: ? cal_sigtr_lwr = cal_drvtn_lwr ? cal_sigtr_upr = cal_drvtn_upr ? code_sigtr_lwr = code_drvtn_lwr ? code_sigtr_upr = code_drvtn_upr signature crc, calibration values, cal_sigtr_lwr table 154 . cal_sigtr_lwr register definitions page addresses default access flash backup 0x04 0x04, 0x05 not applicable r yes table 155 . cal_sigtr_lwr bit definitions bits description [15:0] factory programmed crc value for the program code, low word signature crc, calibration values, cal_sigtr_upr table 156 . cal_sigtr_upr register definitions page addresses default access flash backup 0x04 0x06, 0x07 not applicable r yes table 157 . cal_sigtr_upr bit definitions bits description [15:0] factory programmed crc value for the program code, high word derived crc, calibration values, cal_drvtn_lwr table 158 . cal_drvtn_lwr register definitions pag e addresses default access flash backup 0x04 0x08, 0x09 not applicable r no table 159 . cal_drvtn_lwr bit definitions bits description [15:0] calculated crc value for the program code, low word derived crc, calibration values, ca l_drvtn_upr table 160 . cal_drvtn_upr register definitions page addresses default access flash backup 0x04 0x0a, 0x0b not applicable r no table 161 . cal_drvtn_upr bit definitions bits description [15:0] cal culated crc value for the program code, high word signature crc, program code, code_sigtr_lwr table 162 . code_sigtr_lwr register definitions page addresses default access flash backup 0x04 0x0c, 0x0d not applicable r yes table 163 . code_sigtr_lwr bit definitions bits description [15:0] factory programmed crc value for the calibration coefficients, low word
ADIS16490 data sheet rev. 0 | page 34 of 37 signature crc, program code, code_sigtr_upr table 164 . code_sigtr_upr reg ister definitions page addresses default access flash backup 0x04 0x0e, 0x0f not applicable r yes table 165 . code_sigtr_upr bit definitions bits description [15:0] factory programmed crc value for the calibration coefficients, hi gh word derived crc, program code, code_drvtn_lwr table 166 . code_drvtn_lwr register definitions page addresses default access flash backup 0x04 0x10, 0x11 not applicable r no table 167 . code_drvtn_lwr bit definitions bits description [15:0] calculated crc value for the calibration coefficients, low word derived crc, program code, code_drvtn_upr table 168 . code_drvtn_lwr register definitions page addresses default access flash back up 0x04 0x12, 0x13 not applicable r no table 169 . code_drvtn_upr bit definitions bits description [15:0] calculated crc value for the calibration coefficients, high word lot specific serial number, serial_num table 170 . serial_num register definitions page addresses default access flash backup 0x04 0x20, 0x21 not applicable r yes table 171 . serial_num bit definitions bits description [15:0] lot specific serial number fir filters the ADIS16490 provides four fir filter banks to configure and select for each individual inertial sensor using the f i ltr_bnk_0 (see table 143 ) and f ilt r_bnk_1 (see table 145 ) registers . each fir filter bank (a, b, c, and d) has 120 taps that consume two pages of memory. the coefficient associated with each tap, in each filter bank, has its own dedicated regi ster that uses a 16 - bit, twos complement format. the fir filter has unity gain when the sum of all of the coefficients is equal to 32,768. for filter designs that require less than 120 taps, write 0x0000 to all unused registers to eliminate the latency ass ociated with that particular tap. fir filter bank a, fir_coef_a000 to fir_coef_a119 table 172 . fir filter bank a memory map page page_id address es register 5 0x05 0x00, 0x01 page_id 5 0x05 0x02 to 0x07 not used 5 0x05 0x08, 0x0 9 fir_coef_a000 5 0x05 0x0a, 0x0b fir_coef_a001 5 0x05 0x0c to 0x7d fir_coef_a002 to fir_coef_a058 5 0x05 0x7e, 0x07f fir_coef_a059 6 0x06 0x00, 0x01 page_id 6 0x06 0x02 to 0x07 not used 6 0x06 0x08, 0x09 fir_coef_a060 6 0x06 0x0a, 0x0b fir_coef_a06 1 6 0x06 0x0c to 0x7d fir_coef_a062 to fir_coef_a118 6 0x06 0x7e, 0x7f fir_coef_a119 table 173 and table 174 provide deta iled register and bit definitions for one of the fir coefficient registers in bank a, fir_coef_ a071. table 175 provides a configuration example, which sets this register to a decimal value of ? 169 (0xff57). table 173 . fir_coef_a071 register definitions page addresses default access flash backup 0x06 0x1e, 0x1f not applicable r/w yes table 174 . fir_coef_a071 bit definitions bits description [15:0] fir bank a, coefficient 71, t wos complement table 175 . co nfiguration example, fir coefficient din description 0x8006 turn to page 6 0x9e57 fir_coef_a071[7:0] = 0x57 0x9fff fir_coef_a071[15:8] = 0xff fir filter bank b, fir_coef_b000 to fir_coef_b119 table 176 . filter bank b memory map page page_id address es register 7 0x07 0x00, 0x01 page_id 7 0x07 0x02 to 0x07 not used 7 0x07 0x08, 0x09 fir_coef_b000 7 0x07 0x0a, 0x0b fir_coef_b001 7 0x07 0x0c to 0x7d fir_coef_b002 to fir_coef_b058 7 0x07 0x7e, 0x07f fir_coef_b059 8 0x08 0x00, 0 x01 page_id 8 0x08 0x02 to 0x07 not used 8 0x08 0x08, 0x09 fir_coef_b060 8 0x08 0x0a, 0x0b fir_coef_b061 8 0x08 0x0c to 0x7d fir_coef_b062 to fir_coef_b118 8 0x08 0x7e, 0x7f fir_coef_b119
data sheet ADIS16490 rev. 0 | page 35 of 37 fir filter bank c, fir_ coef_c000 to fir_coef_c119 table 177. filter bank c memory map page page_id addresses register 9 0x09 0x00, 0x01 page_id 9 0x09 0x02 to 0x07 not used 9 0x09 0x08, 0x09 fir_coef_c000 9 0x09 0x0a, 0x0b fir_coef_c001 9 0x09 0x0c to 0x7d fir_coef_c002 to fir_coef_c058 9 0x09 0x7e, 0x07f fir_coef_c059 10 0x0a 0x00, 0x01 page_id 10 0x0a 0x02 to 0x07 not used 10 0x0a 0x08, 0x09 fir_coef_c060 10 0x0a 0x0a, 0x0b fir_coef_c061 10 0x0a 0x0c to 0x7d fir_coef_c062 to fir_coef_c118 10 0x0a 0x7e, 0x7f fir_coef_c119 fir filter bank d, fir_ coef_d000 to fir_coef_d119 table 178. filter bank d memory map page page_id addresses register 11 0x0b 0x00, 0x01 page_id 11 0x0b 0x02 to 0x07 not used 11 0x0b 0x08, 0x09 fir_coef_d000 11 0x0b 0x0a, 0x0b fir_coef_d001 11 0x0b 0x0c to 0x7d fir_coef_d002 to fir_coef_d058 11 0x0b 0x7e, 0x07f fir_coef_d059 12 0x0c 0x00, 0x01 page_id 12 0x0c 0x02 to 0x07 not used 12 0x0c 0x08, 0x09 fir_coef_d060 12 0x0c 0x0a, 0x0b fir_coef_d061 12 0x0c 0x0c to 0x7d fir_coef_d062 to fir_coef_d118 12 0x0c 0x7e, 0x7f fir_coef_d119 default filter performance the fir filter banks have factory programmed filter designs. they are all low-pass filters that have unity dc gain. table 179 provides a summary of each filter design, and figure 47 shows the frequency response characteristics. the phase delay is equal to ? of the total number of taps. table 179. fir filter descript ions, default configuration fir filter bank taps ?3 db frequency (hz) a 120 300 b 120 100 c 32 300 d 32 100 no fir filtering 0 ?10 ?20 magnitude (db) ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 200 400 600 800 1000 1200 frequency (hz) a dc b 15029-031 figure 47. fir filter fr equency response curves
ADIS16490 data sheet rev. 0 | page 36 of 37 applications information mounting best practices for the best performance, follow these simple rules when installing the ADIS16490 into a system: ? eliminate opportunity for translational force (x- and y-axis direction, per figure 37) application on the electrical connector. ? use uniform mounting forces on all four corners. the suggested torque setting is 40 inch ounces (0.285 nm). ? when the imu rests on the pcb, which contains the mating connector (see figure 48), use a diameter of at least 2.85 mm for the passthrough holes. these rules help prevent irregular force profiles, which can warp the package and introduce bias errors in the sensors. figure 48 and figure 49 provide details for mounting hole and connector alignment pin drill locations. device outline 19.800 bsc 39.600 bsc 42.600 21.300 bsc 5 bsc 5 bsc 1.642 bsc notes 1. all dimensions in mm units. 2. in this configuration, the connector is facing down and its pins are not visible. 0.560 bsc 2 alignment holes passthrough hole for mounting screws diameter of the hole must accomodate dimensional tolerance between the connector and holes. for mating socket 15029-033 figure 48. suggested pcb layout pattern, connector down 0.4334 [11.0] 0.0240 [0.610] 0.019685 [0.5000] (typ) 0.054 [1.37] 0.0394 [1.00] 0.0394 [1.00] 0.1800 [4.57] nonplated thru hole 2 0.022 dia (typ) 0.022 dia thru hole (typ) nonplated thru hole 15029-034 figure 49. suggested layout and mechanical design when using samtec clm-112-02-g-d-a for the mating connector preventing misinsertion the ADIS16490 connector uses the same pattern as the adis16485 , but with pin 12 and pin 15 missing. this pin configuration enables a mating connector to plug these holes, which makes inserting the ADIS16490 incorrectly very difficult. samtec has a custom part number that provides this type of mating socket: asp-193371-04. evaluation tools breakout board, adis16imu1/pcbz the adis16imu1/pcbz (sold separately) provides a breakout board function for the ADIS16490 , which means that it provides access to the ADIS16490 through larger connectors that support standard 1 mm ribbon cabling. it also provides four mounting holes for attachment of the ADIS16490 to the breakout board. pc-based evaluation, eval-adis2 use the eval-adis2 and adis16imu1/pcbz to evaluate the ADIS16490 on a pc-based platform. power supply considerations the vdd power supply must charge 46 f of capacitance (inside of the ADIS16490 , across the vdd and gnd pins) during its initial ramp and settling process. when vdd reaches 2.85 v, the ADIS16490 begins its internal start-up process, which gener- ates additional transient current demand. see figure 50 for a typical current profile during the start-up process. the first peak in figure 50 relates to charging the 46 f capacitor bank, whereas the other transient activity relates to numerous functions turning on during the initialization process of the ADIS16490 . 15029-350 ch2 2.0v b w ch3 2.0v b w ch4 100ma b w m40.0ms a ch3 3.00v t 20.10% 12.5ms/s 5m pts 4 3 2 dr vdd current a b t a b 1.608ms 159.8ms 92.00ma 152.0ma ? 158.2ms ? 60.00ma figure 50. transient current demand , startup (dr means data ready)
data sheet ADIS16490 rev. 0 | page 37 of 37 packaging and ordering information outline dimensions 10-20-2016-a bottom view front view top view 44.254 44.000 43.746 34.600 34.575 34.550 39.800 39.600 39.400 20.00 19.80 19.60 47.254 47.000 46.746 37.598 37.573 37.548 42.800 42.600 42.400 2.20 bsc ? 2.40 bsc 2.20 bsc 14.200 14.000 13.800 3.454 3.200 2.946 0.250 bsc 13.750 ref 0.250 bsc 5.50 bsc 5.50 bsc detail a detail a 1.00 bsc pitch 0.30 sq bsc 1.142 bsc ? 2.065 2.040 2.015 2.065 2.040 2.015 47.479 47.379 47.279 3.70 3.50 3.30 7.350 7.225 7.100 2.325 2.200 2.075 2.84 bsc 1 224 23 figure 51. 24-lead module with connector interface [module] (ml-24-9) dimensions shown in millimeters ordering guide model 1 temperature range description package option ADIS16490bmlz ?40c to +105c 24-lead module with connector interface [module] ml-24-9 1 z = rohs compliant part. ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d15029-0-10/16(0)

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